Triggering Trojans in SRAM circuits with X-propagation

Kan, Senwen; Dworak, Jennifer

doi:10.1109/dft.2014.6962105

Cited by 6 publications

(1 citation statement)

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“…A variety of disciplines track the movement of data through hardware designs in order to make important design decisions. For example, information flow tracking (IFT) monitors the propagation of security critical information to determine compliance to security properties [2-4, 8, 14]; X-propagation aims to understand how nondeterministic values originating from uninitialized registers influence reliability and where they could possibly flow to [1,5,6,10,13]; and fault propagation models the effect of faulty values on system reliability [7,11,16] and susceptibility to implementation attacks [9,15].…”

Section: Introductionmentioning

confidence: 99%

A Unified Model for Gate Level Propagation Analysis

Blackstone¹,

Hu²,

Althoff³

et al. 2020

Preprint

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Classic hardware verification techniques (e.g., X-propagation and fault-propagation) and more recent hardware security verification techniques based on information flow tracking (IFT) aim to understand how information passes, affects, and otherwise modifies a circuit. These techniques all have separate usage scenarios, but when dissected into their core functionality, they relate in a fundamental manner. In this paper, we develop a common framework for gate level propagation analysis. We use our model to generate synthesizable propagation logic to use in standard EDA tools. To justify our model, we prove that Precise Hardware IFT is equivalent to gate level X-propagation and imprecise fault propagation. We also show that the difference between Precise Hardware IFT and fault propagation is not significant for 74X-series and '85 ISCAS benchmarks with more than 313 gates and the difference between imprecise hardware IFT and Precise Hardware IFT is almost always significant regardless of size.

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Section: Introductionmentioning

confidence: 99%

A Unified Model for Gate Level Propagation Analysis

Blackstone¹,

Hu²,

Althoff³

et al. 2020

Preprint

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Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation

Kan

Ottavi

Dworak

2015

2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

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This paper proposes a scalable solution for obstructing and detecting malicious activity as well as erroneous events during mission mode operation of untrusted memories. The approach obfuscates data written into a memory and remaps the location of memory contents in a manner difficult for an attacker to predict, making it harder for a Hardware Trojan to be deterministically triggered or controlled by malicious agents. Simultaneously, the approach aids in the detection of soft errors. To our knowledge, this approach is among the first to reconcile SRAM security with SRAM soft error reliability. Simulation data gathered from a production-worthy silicon development environment confirms the viability of our method

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