Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation

Abstract

This paper proposes a scalable solution for obstructing and detecting malicious activity as well as erroneous events during mission mode operation of untrusted memories. The approach obfuscates data written into a memory and remaps the location of memory contents in a manner difficult for an attacker to predict, making it harder for a Hardware Trojan to be deterministically triggered or controlled by malicious agents. Simultaneously, the approach aids in the detection of soft errors. To our knowledge, this approach is among the first to reconcile SRAM security with SRAM soft error reliability. Simulation data gathered from a production-worthy silicon development environment confirms the viability of our method