True influence of wafer-backside copper contamination during the back-end process on device characteristics

Hozawa, Kazuyuki; Miyazaki, Hisashi; Yugami, J.

doi:10.1109/iedm.2002.1175943

Cited by 13 publications

(9 citation statements)

References 7 publications

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“…The copper admixture has caused a slight decrease of optical parameters for the AlSi 1% Cu 0.5% alloy gate in comparison to a pure aluminum gate. Similar degradation mechanism of MOS structures was also observed in the papers [11,12], particularly in electrical characteristics of MOS devices.…”

Section: Resultssupporting

confidence: 81%

Nuclear and Optical Analyses of MOS Devices

et al. 2013

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The characteristic dome-like shape distribution of electric parameters (with the biggest values in the middle and the lowest values in the corners of the gate) has been observed in our investigations. Taking the results of the papers into account, the following hypothesis was drawn: the shape distribution of electrical parameters has been caused by the irregular shape of stress distribution under the metal gate. To prove or deny the assumed hypothesis, a lot of investigations on stress and strain in MOS structures are being performed. The study of the atomic composition of electronic components constitutes the starting point of their characterization. Therefore, in this paper, we present experimental results of hydrogen, oxygen, aluminum, silicon, and copper concentrations in MOS structures carried out by the Rutherford backscattering spectrometry and elastic recoil detection methods. These techniques allow inter alia determination of silicon and oxygen content as a function of the position x on a wafer. On the basis of depth prole elastic recoil detection measurements performed on Al and AlSiCu gates, a much larger hydrogen content in the surface layer for MOS structure with Al gate was conrmed. Copper atoms were detected only in the AlSiCu gate.

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Section: Resultssupporting

confidence: 81%

Nuclear and Optical Analyses of MOS Devices

et al. 2013

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“…The Cu atoms may diffuse into both dielectric and active regions of Si substrate even at a low-temperature assembly process. It causes performance degradation and early breakdown of devices [7], [8]. Therefore, analysis of Cu contamination for the 3-D integration has attracted attention in recent years.…”

Section: Evaluation Of Cu Contamination At Backside Surface Of Thinnementioning

confidence: 99%

Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement

Bea

Lee

Fukushima

et al. 2011

IEEE Electron Device Lett.

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The influence of Cu contamination at backside surface of a thinned wafer in three-dimensional LSI was electrically evaluated by capacitance-time (C-t) measurement. A MOS capacitor was fabricated using a thinned wafer of 50-μm thickness. The (C-t) curves of the MOS capacitor were severely degraded even after initial annealing at 300 • C for 5 min. It means that Cu atoms at the back surface reach the Si-SiO 2 interface of the front surface, and the generation lifetime is significantly reduced. The quantitative relationship between the generation lifetime and surface concentration of Cu atom was evaluated. The (C-t) measurement is a highly promising method to electrically characterize the influence of Cu contamination on device reliability in fabricated LSI wafers.

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“…These Cu atoms may diffuse into both dielectric and active region of Si substrate even at low temperature assembly process. It cause the performance degradation and early breakdown of devices [11], [12]. Therefore, the analysis of Cu contamination for the 3-D integration has been attracted attention in recent years.…”

Section: Introductionmentioning

confidence: 99%

Impacts of Cu Contamination on Device Reliabilities in 3-D IC Integration

Lee

Bea

Ohara

et al. 2014

IEEE Trans. Device Mater. Relib.

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The impacts of Cu contamination from a backside surface of a thinned wafer and Cu via on device reliabilities in 3-D IC integration are electrically evaluated. Intrinsic gettering (IG) layer, which was formed by high density oxygen precipitate, shows excellent Cu retardation characteristics from the backside surface of the thinned wafer. Extrinsic gettering (EG) layer, which was formed by postgrinded dry polish (DP) treatment shows good Cu retardation characteristics compared with other postgrinded treatments. The minimal 30-nm-thick Ta barrier layer in Cu via shows good barrier property to Cu diffusion from Cu via after annealing up to 60 min at 300 • C. However, it is not enough at 400 • C annealing, because the generation lifetime shows significant degradation after the initial annealing for 5 min. The DRAM cell characteristics show severe shortening retention time after an intentional Cu diffusion from the backside of the thinned DRAM chip at relatively low temperature of 300 • C.

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True influence of wafer-backside copper contamination during the back-end process on device characteristics

Cited by 13 publications

References 7 publications

Nuclear and Optical Analyses of MOS Devices

Nuclear and Optical Analyses of MOS Devices

Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient-Capacitance Measurement

Impacts of Cu Contamination on Device Reliabilities in 3-D IC Integration

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