True single phase clock dynamic CMOS circuit technique

Karlsson, Ingrid

doi:10.1109/iscas.1988.14967

Cited by 9 publications

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Drawback of this is high-power dissipation along with low noise margin, charge leakage problem, and charge sharing issues. A new idea with encouraging aspects came into presence and was named as TSPC (True Single-Phase Clock) logic [8][9]. This design style has a dynamic inverter placed at the second stage, as shown in Fig.…”

Section: Dynamic Logic Styles (Single Phase Clocking)mentioning

confidence: 99%

High-Speed and Area Efficient Low-Power Dynamic Parity Generator and Parity Checker

Verma,

Sharma,

Pandey

et al. 2023

Preprint

View full text Add to dashboard Cite

Strategic detection of an error using a parity generator and parity checker is indispensable and enforces the design engineer to optimize upscale performance. Even advanced modern communication systems can have errors due to losses/noise. This paper brings to light the design of the superior high-speed, low-power 3-bit dynamic parity generator and checker. Two, four, eight, and sixteen-bit XOR gates have been implemented using previous and proposed techniques. The proposed true single-phase dynamic XOR gate builds the parity checker and generator circuits. The proposed dynamic XOR gate, designed 3-bit parity generator, and checker circuits are compared with recently reported techniques. All circuits have been simulated using Cadence Specter on 90nm technology parameters and tested up to 1 GHz of clock frequency. Comparison is made to showcase the superiority of the proposed design in terms of power consumption, propagation delay, PDP (93.8%), EDP (98.8%), number of transistors, the figure of merit, and unity noise gain. This new 3-bit dynamic parity generator and checker would add a colossal perspective for a design engineer.

show abstract

Section: Dynamic Logic Styles (Single Phase Clocking)mentioning

confidence: 99%

High-Speed and Area Efficient Low-Power Dynamic Parity Generator and Parity Checker

Verma,

Sharma,

Pandey

et al. 2023

Preprint

View full text Add to dashboard Cite

show abstract

“…These clocks are applied to 128 positive-edge-trigger DFFs, which are implemented by the true single-phase clock [6] circuits, to sample the output pulse P out . Since P out has to drive the DFFs, a buffer is added, whose delay is close to that of an XOR gate.…”

Section: Bubble Error Correction Encoder Digital Error Correctiomentioning

confidence: 99%

An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter

Wang

Lee

Liu

2009

IEEE Trans. Circuits Syst. II

View full text Add to dashboard Cite

An 8-bit 20-MS/s time-domain analog-to-digital data converter (ADC) using the zero-crossing-based circuit technique is presented. Compared with the conventional ADCs, signal processing is executed in both the voltage and time domains. Since no high-gain operational amplifier is needed, this time-domain ADC works well in a low supply voltage. The proposed ADC has been fabricated in a 0.18-μm CMOS process. Its power dissipation is 4.64 mW from a supply voltage of 1.8 V. This active area occupies 1.2 × 0.7 mm 2 . The measured signal-to-noise-distortion ratio achieves 44.2 dB at an input frequency of 10 MHz. The integral nonlinearity is less than ±1.07 LSB, and the differential nonlinearity is less than ±0.72 LSB. This time-domain ADC achieves the effective bits of 7.1 for a Nyquist input frequency at 20 MS/s. Index Terms-Analog-to-digital converter (ADC), delay-locked loop (DLL), time domain, zero-crossing-based circuit (ZCBC).

show abstract

Introduction

Jha¹,

Kundu²

1990

The Kluwer International Series in Engineering and Computer Science

View full text Add to dashboard Cite

True single phase clock dynamic CMOS circuit technique

Cited by 9 publications

References 4 publications

High-Speed and Area Efficient Low-Power Dynamic Parity Generator and Parity Checker

High-Speed and Area Efficient Low-Power Dynamic Parity Generator and Parity Checker

An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter

Introduction

Contact Info

Product

Resources

About