2020
DOI: 10.1007/978-3-030-63393-6_23
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Truly Heterogeneous HPC: Co-design to Achieve What Science Needs from HPC

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Cited by 11 publications
(4 citation statements)
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“…Inside the GPU kernel, threads access a and b pointers from the kernel function parameters. When accessing addresses based on a and b pointers (e.g., a[0], a [1], etc. ), GPU threads emit loads and stores with the host pointer values as the base address.…”
Section: Related Workmentioning
confidence: 99%
See 1 more Smart Citation
“…Inside the GPU kernel, threads access a and b pointers from the kernel function parameters. When accessing addresses based on a and b pointers (e.g., a[0], a [1], etc. ), GPU threads emit loads and stores with the host pointer values as the base address.…”
Section: Related Workmentioning
confidence: 99%
“…High-performance computing (HPC) node architecture designs are driven primarily by power management considerations and are increasingly reliant on high degrees of finegrained parallelism [1], [2]. Top500 list [3] mentions over 150+ known systems that use accelerator/co-processor technology.…”
Section: Introductionmentioning
confidence: 99%
“…When we design an HPC system and environment, multiple scientists, software developers, and hardware developers need to discuss an optimal system with collaborations; hardware based on existing technology and software running on it as well as new hardware and software not yet emerging result in challenging scientific goals (Cardwell et al) [38][39][40]. The best ideal HPC system requires the shared development of actionable information that engages all communities in charge and the values guiding their engagement.…”
Section: Co-designmentioning
confidence: 99%
“…In the context of Edge computing, domain-specific accelerators (ASICs and FPGA) and generalpurpose processors are commonly used together to perform near-data processing, thereby, unlocking various real-time use cases (e.g., edge AI and AR/VR applications) [2], [3]. In the HPC context, deploying various machine types with different architectures on HPC boards to fulfill the power and performance requirements is becoming a trend [7].…”
Section: Introductionmentioning
confidence: 99%