Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

The brain has effectively proven a powerful inspiration for the development of computing architectures in which processing is tightly integrated with memory, communication is event‐driven, and analog computation can be performed at scale. These neuromorphic systems increasingly show an ability to improve the efficiency and speed of scientific computing and artificial intelligence applications. Herein, it is proposed that the brain's ubiquitous stochasticity represents an additional source of inspiration for expanding the reach of neuromorphic computing to probabilistic applications. To date, many efforts exploring probabilistic computing have focused primarily on one scale of the microelectronics stack, such as implementing probabilistic algorithms on deterministic hardware or developing probabilistic devices and circuits with the expectation that they will be leveraged by eventual probabilistic architectures. A co‐design vision is described by which large numbers of devices, such as magnetic tunnel junctions and tunnel diodes, can be operated in a stochastic regime and incorporated into a scalable neuromorphic architecture that can impact a number of probabilistic computing applications, such as Monte Carlo simulations and Bayesian neural networks. Finally, a framework is presented to categorize increasingly advanced hardware‐based probabilistic computing technologies.

Probabilistic computing using random number generators (RNGs) can leverage the inherent stochasticity of nanodevices for system-level benefits. Device candidates for this application need to produce highly random "coinflips" while also having tunable biasing of the coin. The magnetic tunnel junction (MTJ) has been studied as an RNG due to its thermally-driven magnetization dynamics, often using spin transfer torque (STT) current amplitude to control the random switching of the MTJ free layer magnetization, here called the stochastic write method. There are additional knobs to control the MTJ-RNG, including voltage-controlled magnetic anisotropy (VCMA) and spin orbit torque (SOT), and there is need to more systematically study and compare these methods. We build an analytical model of the MTJ to characterize using VCMA and SOT to generate random bit streams. The results show that both methods produce high quality, uniformly distributed bitstreams. Biasing the bitstreams using either STT current or an applied magnetic field shows a sigmoidal distribution vs. bias amplitude for both VCMA and SOT, compared to less sigmoidal for stochastic write. The energy consumption per sample is calculated to be 0.1 pJ (SOT), 1 pJ (stochastic write), and 20 pJ (VCMA), revealing the potential energy benefit of using SOT and showing using VCMA may require higher damping materials. The generated bitstreams are then applied to two tasks: generating an arbitrary probability distribution and using the MTJ-RNGs as stochastic neurons to perform simulated annealing, where both VCMA and SOT methods show the ability to effectively minimize the system energy with small delay and low energy. These results show the flexibility of the MTJ as a true RNG and elucidate design parameters for optimizing the device operation for applications.

No abstract

No abstract