Truncated multiplication with correction constant [for DSP]

High Performance 8-bit Approximate Multiplier using Novel 4:2 Approximate Compressors for Fast Image Processing

“…In this section the proposed multipliers are compared with ten other multipliers: truncated1 [7], truncated2 [8], truncated3 [9], LOA [5], Momeni [15], Ma [16], Liu [13,14], Kulkani [11], Accurate3:2 (the Dadda multiplier constructed by 3:2 precise compressors), and Accurate4:2 (the Dadda multiplier constructed by 4:2 precise compressors). Table 4 shows the MSE, the delay, the number of transistors, and the product of delay and the number of transistors (PDT) of each multiplier.…”

“…In [6], an approximate booth multiplier was proposed which then was used in low-pass finite impulse response and then applied to digital signal processing. In [7], in order to reduce delay and the number of transistors, a truncated multiplier was proposed. In this approximate multiplier, the k least significant bits of partial products are truncated or ignored, and the remaining most significant bits of partial products are added with each other and the result then is added with a constant to compensate the truncation, and the final result is rounded to p bits.…”

Real-time algorithms and architectures for multiuser channel estimation and detection in wireless base-station receivers

“…We assume that a Wallace or Dadda multiplier tree [34] is used for multiplication requiring 1-bit full adders (FA) for an -bit multiplication. Since the multiplication by in (15) (implemented as a shift) results in truncation of the output, a truncated multiplication using significantly less hardware [35] can be used. The delays of blocks such as multiplexers and gates are assumed to be included in the single-cycle delay.…”

A generalized methodology for lower-error area-efficient fixed-width multipliers

“…Concurrently treating method for reduction and rounding errors of Eq. (14) can be directly referred to derivation of [3]. In the first step, to design a realizable error-compensation bias, two types of binary thresholding for the error-compensation bias can be changed to , where A, ND, and FA denote AND gate, NAND gate, and a full adder, respectively, and other main symbolic cells are depicted in Fig.…”

“…However, in his analysis the reduction and rounding errors are separately treated such that this scheme does not lead to an accurate enough error-compensation bias. Schulte et al [3] improved the error-compensation bias to be more accurate and practical since the reduction and rounding errors are concurrently treated. The above two schemes are based on keeping w s columns of the subproduct array, where w is a nonnegative integer between 0 and 1 s .…”