TSV development for miniaturized MEMS acceleration switch

Lietaer, Nicolas; Anand, Srinivasan; Bakke, Thor; Taklo, Maaike M. Visser; Dalsjo, Per

doi:10.1109/3dic.2010.5751457

Cited by 7 publications

(5 citation statements)

References 4 publications

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“…Such an acceleration switch was designed, fabricated, and packaged by applying the proposed capping method in combination with TSV interconnections, as illustrated by the process sequence shown in Figure 2 e–h. A via-first fabrication approach, in which the TSVs are fabricated before the MEMS structures, was employed to create heavily doped polysilicon vias with a footprint of 7 μ

x 70 μ

[ 22 , 28 ]. After the MEMS switch fabrication, the devices were packaged using the glass capping process, and metal pads were fabricated on the back side of the substrate.…”

Section: Resultsmentioning

confidence: 99%

Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

et al. 2016

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Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS) transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS) compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

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x 70 μ

[ 22 , 28 ]. After the MEMS switch fabrication, the devices were packaged using the glass capping process, and metal pads were fabricated on the back side of the substrate.…”

Section: Resultsmentioning

confidence: 99%

Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

et al. 2016

Self Cite

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“…Polysilicon TSV technologies are becoming mature, and several MEMS fabs like Teledyne DALSA (Waterloo, Canada) provide polysilicon TSV foundry services [123]. SINTEF has developed both hollow and solid polysilicon TSVs for interposer applications [124], with the resistance of a typical 7×300 μm TSV being 3 [125]. For polysilicon and W TSVs, annular structures are often used to facilitate filling or deposition of polysilicon or W into high aspect-ratio trenches [126]- [129].…”

Section: B Sidewall Insulationmentioning

confidence: 99%

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Wang

2015

J. Microelectromech. Syst.

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After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore's Law without needing to continuously shrink feature sizes. The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics. This 3-D heterointegration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications. This paper reviews the following aspects of the MEMS/ microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/ microsensor products using 3-D integration technologies. Of particular interest throughout this paper is the heterointegration of the MEMS and CMOS technologies. [2015-0158]Index Terms-Three-dimensional (3-D) integration, microelectromechanical systems (MEMS), microsensor, packaging, hetero-integration, interposer, through-silicon-via (TSV), waferlevel packaging, microsystem.

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“…The earlier work indicated that our bonding process gave reliable vacuum sealing of the individual CMUT cavities, even though the minimum separation between the cavities was a 1.1 μm wide silicon line [9]. We now integrate our CMUT fabrication process [9] with our process for TSV manufacturing [18]. The process for TSV fabrication must be compatible with the CMUT fabrication process, which contains several hightemperature process steps.…”

Section: Cmut Design and Integration Of Cmut And Tsv Processesmentioning

confidence: 99%

Fabrication process for CMUT arrays with polysilicon electrodes, nanometre precision cavity gaps and through-silicon vias

Due-Hansen¹,

Midtbo²,

Poppe³

et al. 2012

J. Micromech. Microeng.

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Capacitive micromachined ultrasound transducers (CMUTs) can be used to realize miniature ultrasound probes. Through-silicon vias (TSVs) allow for close integration of the CMUT and read-out electronics. A fabrication process enabling the realization of a CMUT array with TSVs is being developed. The integrated process requires the formation of highly doped polysilicon electrodes with low surface roughness. A process for polysilicon film deposition, doping, CMP, RIE and thermal annealing that resulted in a film with sheet resistance of 4.0 Ω/□ and a surface roughness of 1 nm rms has been developed. The surface roughness of the polysilicon film was found to increase with higher phosphorus concentrations. The surface roughness also increased when oxygen was present in the thermal annealing ambient. The RIE process for etching CMUT cavities in the doped polysilicon gave a mean etch depth of 59.2 ± 3.9 nm and a uniformity across the wafer ranging from 1.0 to 4.7%. The two presented processes are key processes that enable the fabrication of CMUT arrays suitable for applications in for instance intravascular cardiology and gastrointestinal imaging.

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TSV development for miniaturized MEMS acceleration switch

Cited by 7 publications

References 4 publications

Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

Fabrication process for CMUT arrays with polysilicon electrodes, nanometre precision cavity gaps and through-silicon vias

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