TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs

Miller, Felix; Wild, Thomas; Herkersdorf, Andreas

doi:10.1109/dsd.2012.135

Cited by 11 publications

(5 citation statements)

References 29 publications

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“…Based on the serialization methodology, Pasricha [26] proposed a 3D NoC synthesis framework by augmenting router and placement techniques proposed in [27], these routers have several local ports which have high power consumption due to the increased number of ports and high data rates across the crossbar. On the other hand, existing inhomogeneous architectures [28], [7], [22], [29], [3], [4], [24], [30], [31], [32], [5] assume a fully mapped NoC and do not consider the dynamics of application traffic load in their inhomogeneous architectures [13]. Applications in such 3D NoCs are not optimized as communication bandwidth and performance constraints of the applications were not considered in the architecture generation [13].…”

Section: Related Workmentioning

confidence: 99%

Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

Agyeman

Ahmadinia

Bagherzadeh

2018

Journal of Systems Architecture

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Three dimensional Networks-on-Chip (3D NoCs) have evolved as an ideal solution to the communication demands and complexity of future high density many core architectures. However, the design practicality of 3D NoCs faces several challenges such as thermal issues, high power consumption and area overhead of 3D routers as well as high complexity and cost of vertical link implementation. To mitigate the performance and manufacturing cost of 3D NoCs, inhomogeneous architectures have emerged to combine 2D and 3D routers in 3D NoCs producing lower area and energy consumption while maintaining the performance of homogeneous 3D NoCs. Due to the limited number of vertical links, application mapping on inhomogeneous 3D NoCs can be complex. However, application mapping has a great impact on the performance and energy consumption of NoCs. This paper presents an energy and performance aware application mapping algorithm for inhomogeneous 3D NoCs. The algorithm has been evaluated with various realistic traffic patterns and compared with existing mapping algorithms. Experimental results show NoCs mapped with the proposed algorithm have lower energy consumption and significant reduction in packet delays compared to the existing algorithms and comparable average packet latency with Branch-and-Bound.

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Section: Related Workmentioning

confidence: 99%

Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

Agyeman

Ahmadinia

Bagherzadeh

2018

Journal of Systems Architecture

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“…A TSV is an interconnection that allows connecting layers of 3D integrated circuits [1]. The advantage of TSVs is an enhanced electrical performance and an increased integration density [2].…”

Section: Introductionmentioning

confidence: 99%

A novel efficient TSV built-in test for stacked 3D ICs

Guibane¹,

Hamdi²,

Bensalem³

et al. 2018

Turk J Elec Eng & Comp Sci

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A through-silicon via (TSV) is established as the main enabler for a three-dimensional integrated circuit (3D IC) that increases system density and compactness. The exponential increase in TSV density led to TSV-induced catastrophic and parametric faults. We propose an original architecture that detects errors caused by TSV manufacturing defects. The proposed design for testability is a built-in technique that detects errors in an early manufacturing stage and is hence very economically attractive. The proposal is capable of testing each and every TSV in the network. The technique achieves high fault coverage and high observability.

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“…Serialization of TSVs can contribute to reduction in their number [10]. TSV-virtualization based reduction in the number of TSVs used in 3D-ICs has been reported in [11]. Here, the authors have proposed TSV-virtualization scheme for multi-protocol-interconnect in 3D-ICs.…”

Section: Introductionmentioning

confidence: 99%

Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip

Manna

Chattopadhyay

Sengupta

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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This paper presents a combined solution to the Through-Silicon-Via (TSV) placement and mapping of cores to routers in a three-dimensional Network-on-Chip (NoC) design. It takes care of TSV geometries and communication requirements between cores. Comparison has been carried out with the recent 3D mapping results. Both static and dynamic performance have been considered. It shows that an intelligent placement of TSVs coupled with mapping can improve the performance significantly.

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TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs

Cited by 11 publications

References 29 publications

Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

A novel efficient TSV built-in test for stacked 3D ICs

Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip

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