Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

Japa, Aditya; Majumder, Manoj Kumar; Sahoo, Subhendu Kumar; Vaddi, Ramesh

doi:10.1002/cta.2731

Cited by 5 publications

(3 citation statements)

References 34 publications

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“…[ 160 ] Additionally, an all‐spin logic device which utilized the variation in magnetization direction to change the circuit functionality without changing the overall device structure was also successfully demonstrated. [ 161 ] Other obfuscation techniques involving TFETs, [ 162 ] amorphous resistance change in PCM cells, [ 163 ] intrinsic stochasticity and polymorphism of giant spin‐Hall effect (GSHE) switches, [ 164 ] and ferroelectric active interconnects [ 165 ] have also been successful. More recently, independent from exploiting defects, obfuscation techniques based on 2D materials such as graphene, BP, and TMDs which rely on the intrinsic ambipolar transport and the substitutional doping of channel materials have been demonstrated.…”

Section: D‐material‐based Camouflagingmentioning

confidence: 99%

“…SiNW FETs [212] Tunable polarity Camouflaging Low area Limited subthreshold swing TFET [162,212] p-i-n forward current/tunable polarity Camouflaging/TRNG Resilience to RE attacks, low power and compact Low ON current and high capacitance effects PCM [163] Cell resistance variation Camouflaging/TRNG/PUF/ tamper detection Resilience to imaging (SEM), low area High-programming current values GSHE [164] Tunable stochastic nature Camouflaging Resilient to Boolean SAT attacks Limited reliability and retention 2D materials [5,16,118] variations, in addition to their resilience against ML attacks based on Fourier regression models and adversarial DNNs. Finally, the future outlook of 2D technology was discussed along with its current status, challenges, mitigation strategies, and their possible implications toward developing secure hardware platforms. )…”

Section: High Write and Current Valuesmentioning

confidence: 99%

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Hardware and Information Security Primitives Based on 2D Materials and Devices

Wali

Das

2023

Advanced Materials

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Hardware security is a major concern for the entire semiconductor ecosystem that accounts for billions of dollars in annual losses. Similarly, information security is a critical need for the rapidly proliferating edge devices that continuously collect and communicate a massive volume of data. While silicon‐based complementary metal‐oxide‐semiconductor technology offers security solutions, these are largely inadequate, inefficient, and often inconclusive, as well as resource intensive in time, energy, and cost, leading to tremendous room for innovation in this field. Furthermore, silicon‐based security primitives have shown vulnerability to machine learning (ML) attacks. In recent years, 2D materials such as graphene and transition metal dichalcogenides have been intensely explored to mitigate these security challenges. In this review, 2D‐materials‐based hardware security solutions such as camouflaging, true random number generation, watermarking, anticounterfeiting, physically unclonable functions, and logic locking of integrated circuits (ICs) are summarized with accompanying discussion on their reliability and resilience to ML attacks. In addition, the role of native defects in 2D materials in developing high entropy hardware security primitives is also examined. Finally, the existing challenges for 2D materials, which must be overcome for large‐scale deployment of 2D ICs to meet the security needs of the semiconductor industry, are discussed.

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Section: D‐material‐based Camouflagingmentioning

confidence: 99%

Section: High Write and Current Valuesmentioning

confidence: 99%

Hardware and Information Security Primitives Based on 2D Materials and Devices

Wali

Das

2023

Advanced Materials

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“…32,33 Orthogonal to this, the p-i-n forward current of TFET is explored as favorable feature to enhance the hardware security of circuits/systems. [34][35][36] In the recent works, authors have proposed TFET p-i-n forward based TRNG design that shows higher resilience towards reverse engineering attacks. 34 Leveraging the p-i-n forward current, TFET-based differential power analysis resistant crypto circuits have been demonstrated that achieve lower area overhead.…”

Section: Introductionmentioning

confidence: 99%

Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

Japa

Majumder

Sahoo

et al. 2021

Circuit Theory & Apps

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Conventional complementary metal oxide semiconductor (CMOS)-based dedicated true random number generator (TRNG) and physically unclonable function (PUF) designs have exhibited higher energy consumption and large area overhead with technology scaling. In contrast, this paper for the first time presents emerging tunnel field-effect transistor (TFET)-based ultra-lightweight reconfigurable TRNG and PUF design. A unique methodology is proposed that considers p-i-n forward current characteristics to generate random keys for PUF and TRNG designs. Leveraging the p-i-n forward current of TFET, a ring oscillator (RO) is designed that exhibits variation in the operating frequency and acts as the main source of entropy for both PUF and TRNG. The TRNG in the proposed design is robust and passed all the National Institute of Standards and Technology (NIST) tests. Considering the variation in p-i-n forward current, the uniqueness of PUF is calculated as 47.5% and 46% at a supply voltage of 0.5 and 0.45 V, respectively. Moreover, PUF achieves high reliability of 82% and 88.7% with supply voltage and temperature variations, respectively. The proposed design is proved to be compact with relatively lower gate count and shows low energy consumption of 4.8 pJ/bit at 0.5-V supply voltage. With these performance metrics, the proposed design is highly suitable for resourceconstrained internet of things (IoT). K E Y W O R D Sinternet of things (IoT), physically unclonable function (PUF), p-i-n forward leakage, true random number generator (TRNG), tunnel field-effect transistor (TFET)

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Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption

Japa

Sahoo²,

Vaddi³

et al. 2022

J Comput Electron

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Present CMOS technology with scaled channel lengths exhibited higher energy consumption in designing secure electronic circuits against hardware vulnerabilities and breaches. Specifically, CMOS sense amplifier based secure differential power analysis (DPA) countermeasures at scaled channel lengths show large energy consumption with increased vulnerability. Additionally, spin transfer torque magnetic tunnel junction (STT-MTJ) and CMOS based logic-in-memory (LiM) cells demonstrate high energy consumption due to the large write current requirement of STT-MTJ and poor MOS device performance at scaled channel lengths. This paper for the first time leverages emerging tunnel FET (TFET) steep-slope device characteristics and compatible non-volatile STT-MTJ devices for enhanced hardware security with ultra-low energy consumption at lower supply voltages. TFET based sense amplifier based logic (SABL) gates have been proposed that achieve 3× lower energy consumption compared to Si FinFET SABL designs. Further, utilizing TFET SABL gates, TFET Pride S-box is designed that exhibits higher DPA resilience with 3.2× lower energy consumption compared to FinFET designs. With resulted lower static power consumption, TFET SABL based crypto systems can show lower vulnerability to static power side-channel attacks. Besides, proposed STT-MTJ and TFET LiM gates achieves 4× lower energy consumption compared to STT-MTJ and FinFET designs. Moreover, these gates have been explored in logic encryption/locking technique that shows 3.1× lower energy consumption compared to STT-MTJ and FinFET based design. KeywordsTunnel FET (TFET) • Differential power analysis (DPA) • Sense amplifier based logic (SABL) • Spin transfer torque magnetic tunnel junction (STT-MTJ) • Logic-in-memory (LiM) • Logic encryption/locking

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Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

Cited by 5 publications

References 34 publications

Hardware and Information Security Primitives Based on 2D Materials and Devices

Hardware and Information Security Primitives Based on 2D Materials and Devices

Tunnel FET‐based ultra‐lightweight reconfigurable TRNG and PUF design for resource‐constrained internet of things

Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption

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