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This study presents a true random number generator (TRNG) harvesting random bits from delay variations of ambipolarity-based ring oscillator, designed using 20 nm InAs Tunnel FET (TFET). Exploiting the TFET transmission gate (TG) functional failure, TFET ambipolarity-based ring oscillator design has been proposed. Random variations are observed in the oscillating frequency of proposed ring oscillator by changing the TFET device ambipolarity. Exploring the same, a TFET ambipolarity-based TRNG circuit has been demonstrated. XOR gate-based post-processing unit is designed to further enhance the unpredictability and randomness of the output bits. The proposed TRNG has passed various NIST tests performed at a supply voltage of 0.5 V. In 20 nm, the proposed TFET TRNG has an area as low as 90 pm 2 and consumes 5.4 pJ/bit at 0.5 V supply voltage. Ambipolarity-based circuit design makes the proposed TRNG robust against reverse engineering attacks.

This paper presents the design insights and benchmarking of 20nm Hetero-junction Tunnel transistor (HTFET) as steep slope device for designing energy efficient logic gates. 20nm Si FinFET technology has been used for benchmarking HTFET circuit performance. The HTFET logic topologies have improved robustness and energy efficiency over Si FinFET topology, particularly for small supply voltages. This work further explores the analysis of HTFET based cascaded chain of inverters to drive a large capacitive load. It has been demonstrated that HTFET based circuit design opens path for energy efficient logic design not achievable with CMOS technology at small supply voltages.

Summary Tunnel field‐effect transistor (TFET) exhibits significant p‐i‐n forward leakage with the increase in drain‐to‐source voltage bias, and this adversely impacts the power consumption and reliability of TFET digital circuits. This work presents low‐power circuit techniques that result in novel compact gates and recommends tristate gates to mitigate the leakage effects. The proposed novel compact gates and tristate gates demonstrate two and six times lower power consumption compared with conventional TFET transmission gates with enhanced reliability. Further, this work introduces a new design methodology that leverages TFET p‐i‐n forward leakage for hardware obfuscation applications. Utilizing the proposed design methodology, the optimization of 40% and 80% in area and power consumption of hardware security primitives like true random number generators is also accomplished.

Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS-based DPA countermeasures resulted in high area overhead and performance degradation. This study presents low area overhead DPA countermeasure exploring tunnel field effect transistors (TFET) based random number generator (RNG). TFET exhibits significant p-in forward current with an increase in negative drain-to-source voltage bias. It is demonstrated that TFET transmission gate exhibits unconventional behaviour due to p-in forward current of the device. Leveraging this behaviour TFET RNG is designed that extracts random bits from delay variations of the TFET ring oscillator. The proposed TFET RNG achieves low area overhead when compared with the baseline CMOS designs. The proposed DPA countermeasure is demonstrated by integrating the original TFET substitution box (S-box) and TFET RNG. The proposed architecture is found to be resilient to DPA attack and the area overhead of single S-box and Advanced Encryption Standard AES is as low as 12 and 5%, respectively. Apart from low area overhead, the TFET designs with inherent device characteristics show high robustness against reverse engineering attacks which provide a higher level of security to TFET-based circuits and systems.