Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities

Majumder

Sahoo

et al. 2020

Circuit Theory & Apps

Self Cite

Summary Tunnel field‐effect transistor (TFET) exhibits significant p‐i‐n forward leakage with the increase in drain‐to‐source voltage bias, and this adversely impacts the power consumption and reliability of TFET digital circuits. This work presents low‐power circuit techniques that result in novel compact gates and recommends tristate gates to mitigate the leakage effects. The proposed novel compact gates and tristate gates demonstrate two and six times lower power consumption compared with conventional TFET transmission gates with enhanced reliability. Further, this work introduces a new design methodology that leverages TFET p‐i‐n forward leakage for hardware obfuscation applications. Utilizing the proposed design methodology, the optimization of 40% and 80% in area and power consumption of hardware security primitives like true random number generators is also accomplished.

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

Majumder

Sahoo

et al. 2020

Circuit Theory & Apps

Self Cite

“…Due to high current efficiency (g m /I d ) and unity gain frequency, benefits of TFET for ultra-low power analogue and RF circuit designs/ applications were also highlighted [23][24][25][26]. The significance of TFET devices grabbed the attention of designers to explore the device properties for hardware security applications [27][28][29]. Earlier, low-cost TFET-based polymorphic logic circuits were designed to avoid IP cloning [27].…”

Section: Introductionmentioning

confidence: 99%

Tunnel FET ambipolarity‐based energy efficient and robust true random number generator against reverse engineering attacks

IET Circuits, Devices & Systems

Majumder

Sahoo

et al. 2019

Self Cite

This study presents a true random number generator (TRNG) harvesting random bits from delay variations of ambipolarity-based ring oscillator, designed using 20 nm InAs Tunnel FET (TFET). Exploiting the TFET transmission gate (TG) functional failure, TFET ambipolarity-based ring oscillator design has been proposed. Random variations are observed in the oscillating frequency of proposed ring oscillator by changing the TFET device ambipolarity. Exploring the same, a TFET ambipolarity-based TRNG circuit has been demonstrated. XOR gate-based post-processing unit is designed to further enhance the unpredictability and randomness of the output bits. The proposed TRNG has passed various NIST tests performed at a supply voltage of 0.5 V. In 20 nm, the proposed TFET TRNG has an area as low as 90 pm 2 and consumes 5.4 pJ/bit at 0.5 V supply voltage. Ambipolarity-based circuit design makes the proposed TRNG robust against reverse engineering attacks.

Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption

Sahoo²,

Vaddi³

et al. 2022

J Comput Electron

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Present CMOS technology with scaled channel lengths exhibited higher energy consumption in designing secure electronic circuits against hardware vulnerabilities and breaches. Specifically, CMOS sense amplifier based secure differential power analysis (DPA) countermeasures at scaled channel lengths show large energy consumption with increased vulnerability. Additionally, spin transfer torque magnetic tunnel junction (STT-MTJ) and CMOS based logic-in-memory (LiM) cells demonstrate high energy consumption due to the large write current requirement of STT-MTJ and poor MOS device performance at scaled channel lengths. This paper for the first time leverages emerging tunnel FET (TFET) steep-slope device characteristics and compatible non-volatile STT-MTJ devices for enhanced hardware security with ultra-low energy consumption at lower supply voltages. TFET based sense amplifier based logic (SABL) gates have been proposed that achieve 3× lower energy consumption compared to Si FinFET SABL designs. Further, utilizing TFET SABL gates, TFET Pride S-box is designed that exhibits higher DPA resilience with 3.2× lower energy consumption compared to FinFET designs. With resulted lower static power consumption, TFET SABL based crypto systems can show lower vulnerability to static power side-channel attacks. Besides, proposed STT-MTJ and TFET LiM gates achieves 4× lower energy consumption compared to STT-MTJ and FinFET designs. Moreover, these gates have been explored in logic encryption/locking technique that shows 3.1× lower energy consumption compared to STT-MTJ and FinFET based design. KeywordsTunnel FET (TFET) • Differential power analysis (DPA) • Sense amplifier based logic (SABL) • Spin transfer torque magnetic tunnel junction (STT-MTJ) • Logic-in-memory (LiM) • Logic encryption/locking