Two-dimensional analytical model for asymmetric dual-gate tunnel FETs

Abstract

An analytical model for asymmetric dual-gate (ADG) tunnel field-effect transistors (TFETs) combining a TFET with a junctionless field-effect transistor (JL FET) is presented and investigated extensively for the first time in this paper, with the aim of addressing the challenges of conventional DG TFETs. The drain current is composed of the tunneling current of TFET and the drift-diffusion current of JL FET, which leads to high drain current. The model also predicts the impacts of the lengths of the source and intrinsic regions on the potential and drain current. The results show that ADG TFET can generate optimum results (in terms of on-state current I on and on-to-off current ratio I on/I off) compared with the conventional DG TFET, higher I on of 129 µA/µm and a larger I on/I off of 2.1 × 1010 are obtained when the optimized lengths of the source and intrinsic regions are almost 14 nm. Very good agreements for both the potential and the drain current are observed between the model calculations and the simulated results.