A two-dimensional analytical model for hetero-junction double-gate tunnel FETs (DG TFETs) with a stacked gate-oxide structure is proposed in this paper. The effects of both the channel mobile charges and source/drain depletion regions on the channel potential profile are considered for the higher accuracy of the proposed model. Poisson’s equation is solved using the superposition principle and Fourier series solution to model the channel potential. The band-to-band tunneling generation rate is expressed as a function of the channel electric field derived from the channel potential and then integrated analytically to derive the drain current of the hetero-junction DG TFETs with a stacked gate-oxide structure using the shortest tunneling path. The effects of device parameters on the channel potential, drain current, and transconductance are investigated. Very good agreements are observed between the model calculations and the simulated results.

An analytical model for a dual-material control-gate (DMCG) tunnel field effect transistor (TFET) is presented for the first time in this paper, and the influence of the mobile charges on the potential profile is taken into account. On the basis of the potential profile, the lateral electric field is derived and the expression for the drain current is obtained by integrating the band-to-band tunneling (BTBT) generation rate applicable to low-bandgap and high-bandgap materials over the tunneling region. The model also predicts the impacts of the control-gate work function on the potential and drain current. The advantage of this work is that it not only offers physical insight into device physics but also provides the basic designing guideline for DMCG TFETs, enabling the designer to optimize the device in terms of the on-state current, the on–off current ratio, and suppressed ambipolar behavior. Very good agreements for both the potential and drain current are observed between the model calculations and the simulated results.

An analytical model for asymmetric dual-gate (ADG) tunnel field-effect transistors (TFETs) combining a TFET with a junctionless field-effect transistor (JL FET) is presented and investigated extensively for the first time in this paper, with the aim of addressing the challenges of conventional DG TFETs. The drain current is composed of the tunneling current of TFET and the drift-diffusion current of JL FET, which leads to high drain current. The model also predicts the impacts of the lengths of the source and intrinsic regions on the potential and drain current. The results show that ADG TFET can generate optimum results (in terms of on-state current I on and on-to-off current ratio I on/I off) compared with the conventional DG TFET, higher I on of 129 µA/µm and a larger I on/I off of 2.1 × 1010 are obtained when the optimized lengths of the source and intrinsic regions are almost 14 nm. Very good agreements for both the potential and the drain current are observed between the model calculations and the simulated results.