Two-dimensional analytical model for hetero-junction double-gate tunnel field-effect transistor with a stacked gate-oxide structure

Abstract

A two-dimensional analytical model for hetero-junction double-gate tunnel FETs (DG TFETs) with a stacked gate-oxide structure is proposed in this paper. The effects of both the channel mobile charges and source/drain depletion regions on the channel potential profile are considered for the higher accuracy of the proposed model. Poisson’s equation is solved using the superposition principle and Fourier series solution to model the channel potential. The band-to-band tunneling generation rate is expressed as a function of the channel electric field derived from the channel potential and then integrated analytically to derive the drain current of the hetero-junction DG TFETs with a stacked gate-oxide structure using the shortest tunneling path. The effects of device parameters on the channel potential, drain current, and transconductance are investigated. Very good agreements are observed between the model calculations and the simulated results.

Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance

“…However, the FinFET, having a multi-gate structure, has a limitation in scaling down at a technology node of 5 nm or less, so the introduction of a GAA type MOSFET structure is being considered to improve the gate control capability [1,2]. As well as such a multi-gate architecture, various device structures using a junction-less transistor structure or a channel material other than silicon have been proposed for various applications [3][4][5][6].…”

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

“…Another merit of high-k dielectric engineering is the reduction of SS due to enhanced gate coupling [9]. The stacking of high-k over Silicon introduces defects and lattice mismatches [10]. One of the most promising method to improve the performance with the help of dielectric engineering is stacking the gate oxide layer with high-k material over low-k material [10].…”

“…The stacking of high-k over Silicon introduces defects and lattice mismatches [10]. One of the most promising method to improve the performance with the help of dielectric engineering is stacking the gate oxide layer with high-k material over low-k material [10]. V.P Hu et.al [11] proposed NC vertical hetero-junction TFET with gate to source overlap, but it lacks an analytical model.…”

“…The increased gate capacitance which has exponential dependency with drain current [12] is the reason for the augmented performance. The higher gate controllability and coupling leads to electric field enhancement and this in turn reduces the minimum tunneling length [10]. By incorporating the aforementioned performance improvement methods, a novel structure of NC-DG-HJ TFET is proposed.…”

“…Fig10 shows the comparison of output characteristics of proposed NC TFET and its unstacked counterpart for V G =1.2V. It also compares the models based on TLA method and shortest tunneling approach.…”