Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance

Kim, Ye-Ji; Seon, Yoongeun; Kim, Soo-Won; Kim, Jongmin; Bae, Saemin; Yang, I.Y.; Yoo, Chung Sik; Ham, Junghoon; Hong, Joon Hee; Jeon, Jongwook

doi:10.3390/electronics10101177

Cited by 7 publications

(4 citation statements)

References 30 publications

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“…In 2020, A. D. Gaidhane quasi ballistic transport exacerbated the capacitance matching in NC GAA-FET compared to that in the drift-diffusion only case [106]. In 2021, Jongwook Jeon et al proposed a compact model of NC GAA-FET describing current-voltage (I-V) with interface trap effects considered for the first time, and the proposed model showed good alignment with the results of implicit numerical calculations [107].…”

Section: A Simulation Status Of Nc Gaa-fetmentioning

confidence: 99%

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Qin

Wei

et al. 2023

IEEE Access

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With transistors scaling down to 3 nm node and beyond, short channel effect (SCE) as well as power consumption dissipation present immense challenges for further scaling down of the transistor. Hence the Gate all around field effect transistor (GAA-FET) is proposed to replace the Fin field effect transistor (FinFET) in 3 nm technology node and beyond due to its better gate control over the channel with surrounding gate structure, thus providing improved SCE constraint ability. Traditional transistors suffer from the problems of "Boltzmann Tyranny" and cannot overcome the subthreshold swing (SS) limit of 60 mV/dec at room temperature. To maintain high Ion and avoid Ioff from increasing too much, supply voltage (VDD) of the conventional transistor cannot scale down proportionally with the dimension of the transistor. The concept of negative capacitance (NC) has been demonstrated to be able to obtain sub-60 mV/dec SS with the ability of amplifying the potential of the channel region without VDD increment. The novel device structure of negative capacitance gate all around field effect transistor ( NC GAA-FET) can combine both the advantages of GAA-FET and NC-FET, and is the most promising ultra-low power consumption device and promises to sustain the Moore's law further beyond what is predicted now. Whereas, according to our knowledge, there have been few review papers about NC GAA-FET till now. Herein, we summarize the recent advances of the NC GAA-FET both in simulation and experimental aspects, which we believe will bring about profound changes to the further development of NC GAA-FET devices.INDEX TERMS Negative capacitance effect, short channel effect, subthreshold swing, power consumption dissipation, negative capacitance gate all around field effect transistor.

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Section: A Simulation Status Of Nc Gaa-fetmentioning

confidence: 99%

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Qin

Wei

et al. 2023

IEEE Access

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“…SS is the alteration in the gate voltage for each decade of change of drain current and is given as [32]…”

Section: Temperature-dependent Compact Modellingmentioning

confidence: 99%

“…SS is the alteration in the gate voltage for each decade of change of drain current and is given as [32] SSfalse(Tfalse)=normal∂VnormalGSnormal∂log10ID=normal∂VnormalGSnormal∂ϕnormalSPnormal∂ϕnormalSPnormal∂log10ID=normal∂VnormalGSnormal∂ϕnormalSPkTqln⁡10=(1+CSCnormalFE)kTqln⁡10,where CSand CnormalFE represent the semiconductor and ferroelectric capacitances, respectively.…”

Section: Temperature-dependent Compact Modellingmentioning

confidence: 99%

Impact of temperature on a ferroelectric interfaced negative capacitance double gate junctionless accumulation mode field effect transistor-compact model

2023

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Ferroelectric interfaced negative capacitance field effect transistors are gaining popularity for low power applications; however, as temperature is a constant influencing factor, further study is required to comprehend how these devices are influenced. Through a proposed compact model, this paper analytically investigates the influence of temperature on a ferroelectric interfaced negative capacitance double gate junctionless accumulation mode field effect transistor. This device integrates the benefits of negative capacitance with the junctionless accumulation mode structure. An extensive comparison of the proposed device is made with the existing structure to evaluate the benefits offered by the ferroelectric layer at different temperatures. The Landau–Khalatnikov equation and Pao–Sah integral are employed to obtain the surface potential and drain current model with temperature variation. Various key parameters of the device have been analysed extensively by varying the temperature from 200 to 500 K. It has been found that internal voltage amplification declines as temperature rises, but the sub-threshold swing increases from 46 to 72 mV decade −1 with an increase in temperature. Additionally, with a progressive rise in temperature, the loss of gain and degradation of gate capacitance are observed.

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“…Salahuddin and Datta 17 claimed that introducing a ferroelectric insulator into standard FETs can also bypass the lower voltage operation limit, resulting in a significant gain and amplified voltage 18,19 . Numerous types of research have been extensively investigated to analyze the behavior of FE‐FETs, and different topologies have already been developed and researched for a better understanding of the core characteristic of negative capacitance, including metal ferroelectric insulator semiconductor (MFIS), metal ferroelectric metal insulator semiconductor (MFMIS), double gate negative capacitance FET (DGNCFET), double gate ferroelectric junctionless (DGFJL) transistor, and negative capacitance TFET (NCTFET) 20–23 . The hysteresis transition at the source end dipole, that is, the capacitance divider produced thereby ferroelectric and internal MOS capacitances, determines the beginning of hysteresis in MFIS 24 .…”

Section: Introductionmentioning

confidence: 99%

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

Yadav,

Rewari,

Pandey

2023

Int J Numerical Modelling

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An analytical drain current model for double gate junctionless accumulation mode negative capacitance field effect transistor (DG‐JAM‐NC‐FET) has been developed, combining the merits of junctionless accumulation mode and negative capacitance effect such as fabrication feasibility, low power dissipation, and reduced degradation in mobility. The novelty manifested in our work is because of the incorporation of the JAM structure in ferroelectric‐based negative capacitance FET. The benefit of JAM over existing FETs is that it combines the benefits of the junctionless transistor (JLT) and conventional FETs. It avoids excessive parasitic resistance due to stronger doping in the source and drain areas, resulting in higher conductivity and better characteristics than JLT. An analytical surface potential and threshold voltage have been developed using Poisson's equation and Landau Khalatnikov's (L‐K) equation. The drain current is then determined by integrating the mobile charge using the Pao–Sah integral. Various critical parameters such as surface potential, gain, capacitance, mobile charge density, drain current, threshold voltage, subthreshold swing, transconductance, and the switching ratio have been assessed extensively by varying ferroelectric layer and channel layer thicknesses, respectively. The ON current increases with the increase in ferroelectric thickness due to the voltage amplification given by the ferroelectric layer, and the switching curve gets steeper. The analytical modeling is done in MATLAB, and its comparison is made with the TCAD numerical simulation. The obtained analytical results and the numerical simulation results correspond well.

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Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance

Cited by 7 publications

References 30 publications

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Impact of temperature on a ferroelectric interfaced negative capacitance double gate junctionless accumulation mode field effect transistor-compact model

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

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