In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.

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Ferroelectric interfaced negative capacitance field effect transistors are gaining popularity for low power applications; however, as temperature is a constant influencing factor, further study is required to comprehend how these devices are influenced. Through a proposed compact model, this paper analytically investigates the influence of temperature on a ferroelectric interfaced negative capacitance double gate junctionless accumulation mode field effect transistor. This device integrates the benefits of negative capacitance with the junctionless accumulation mode structure. An extensive comparison of the proposed device is made with the existing structure to evaluate the benefits offered by the ferroelectric layer at different temperatures. The Landau–Khalatnikov equation and Pao–Sah integral are employed to obtain the surface potential and drain current model with temperature variation. Various key parameters of the device have been analysed extensively by varying the temperature from 200 to 500 K. It has been found that internal voltage amplification declines as temperature rises, but the sub-threshold swing increases from 46 to 72 mV decade −1 with an increase in temperature. Additionally, with a progressive rise in temperature, the loss of gain and degradation of gate capacitance are observed.

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