Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints

Abstract

Abstract-Present day market demand for high-performance high-density portable hand-held applications has shifted the focus from 2-D planar system-on-a-chip-type single-chip solutions to alternatives such as tiled silicon and single-level embedded modules as well as 3-D die stacks. Among the various choices, finding an optimal solution for system implementation deals usually with cost, performance, power, thermal, and technological tradeoff analyses at the system conceptual level. It has been estimated that decisions made in the first 20% of the design cycle influence up to 80% of the final product cost. In this paper, we discuss realistic metrics appropriate for performance and cost tradeoff analyses both at the system conceptual level in the early stages of the design cycle and in the implementation phase, for verification. In order to validate the proposed metrics and methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and the performance tradeoffs discussed. This case study is used to highlight the importance of a cost and performance tradeoff analysis early in the design flow.Index Terms-Die stacking, performance and cost tradeoffs, power consumption, system-in-package (SiP), system-on-chip (SoC), system-on-package (SoP), thermal analysis, wafer-level integration (WLI), 3-D integration.

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

“…For a microbump [20] and an ESD protection circuit [22], capacitive loads of 10 and 20 fF are assumed, respectively. For an on-chip metal wire and a buffer, all the parasitic capacitances and resistances data at a 65-nm technology node are obtained from [66] and scaled to each fabrication technology node used in the experiments (i.e., 65-, 45-, and 32-nm technology nodes). The method of using Elmore delay model is suitable to estimate interconnect performance at the early stages of design flow where all the TABLE IV ARCHITECTURE CONFIGURATIONS FOR GRAPHITE SIMULATOR TABLE V BENCHMARK PROGRAMS IN THREE TEST PROGRAM SUITS logics are not synthesized yet, because the design tools for the TSV and the 3-D technology we used are not publicly available.…”

“…The method of using Elmore delay model is suitable to estimate interconnect performance at the early stages of design flow where all the TABLE IV ARCHITECTURE CONFIGURATIONS FOR GRAPHITE SIMULATOR TABLE V BENCHMARK PROGRAMS IN THREE TEST PROGRAM SUITS logics are not synthesized yet, because the design tools for the TSV and the 3-D technology we used are not publicly available. The same method was already used and verified in [66] and [75] for estimating interconnect performance of 3-D ICs. Especially in [75], delay estimation using the firstorder Elmore model for 3-D cache memory has been validated by the Cadence Spectre [76] simulation of a four-way 18-Mb Intel SRAM cache at the 180-nm technology node, achieving an accuracy within 10% of the Cadence simulation result.…”

Pipelined Execution of Windowed Image Computations

“…Newer technologies such as optical and 3-D interconnects [13,15,16] will support a larger value n. On one hand, this will admit a larger value of z for efficient operation. This, coupled with increasing processing capabilities, would allow for larger images to be handled without significant impact on processing time.…”

High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires

“…Not only do 3D-SiPs decrease costs by reducing the volume and weight of the package, but they also improve system performance through enhanced signal transmission speed and lower power consumption which is of importance for various demanding applications [1,2]. This is due primarily to the shorter signal path lengths and lower capacitive, resistive and inductive parasitic components that are enabled by TSVs [3]. 3D-SiP implementations require vertical interconnects through selected dies in the stack in order to connect their functional layers.…”