Two-dimensional photo-mapping on CMOS single-photon avalanche diodes

Abstract

Two-dimensional (2-D) photo-count mapping on CMOS single photon avalanche diodes (SPADs) has been demonstrated. Together with the varied incident wavelengths, the depth-dependent electric field distribution in active region has been investigated on two SPADs with different structures. Clear but different non-uniformity of photo-response have been observed for the two studied devices. With the help of simulation tool, the non-uniform photo-counts arising from the electric field non-uniformity have been well explained. As the quasi-3D distribution of electric field in the active region can be mapped, our method is useful for engineering the device structure to improve the photo-response of SPADs.

A first single-photon avalanche diode fabricated in standard SOI CMOS technology with a full characterization of the device

“…At the same time, however, there are also some disadvantages: lower and narrower PDP as well as higher tunneling noise due to higher doping concentrations. In order to compare performance of the proposed SPAD fabricated in 140-nm SOI CMOS technology to the literature in similar technology nodes, we restricted our attention to all reported substrate-isolated SPADs implemented in a feature size smaller than 250 nm [4,[13][14][15][16][17][18]. Consequently, SPADs fabricated in 350-nm CMOS technology are excluded in this comparison, although they exhibit good performance [19][20][21].…”

“…10. Charbon, 65-nm CMOS [18] Niclass, 130-nm CIS [15] Gersback, 130-nm CIS [16] This work, 140-nm SOI CMOS Veerappan, 180-nm CMOS [4] Leitner, 180-nm CIS [14] Wu, 250-nm HV CMOS [13] Richardson, 130-nm CIS [17] Photon detection probability [ The performance of the SPAD implemented in the standard 140-nm SOI CMOS technology reported in this paper is summarized in Table 1. In addition, it reports a performance comparison with substrate-isolated SPADs fabricated in advanced CMOS technologies (140-nm technology nodes and below).…”

Front-End Electronics for Silicon Photomultipliers

“…Further, the device's noise performance, compared with the state of the art in Figure 8.11, shows that the noise performance attained in this work is better than most of the CMOS SPADs, and it is comparable with the devices that are presented Excess bias (V) Dark count rate per micrometer square Webster 130 nm [82] Bronzi 350 nm [93] Leitner 180 nm [92] Wu 250 nm [94] Richardson 130 nm [30] Niclass 350 nm [3] Mandai 180 nm [83] Niclass 130 nm [79] Gersbach 130 nm [78] is work 180 nm in [94] and [82]. A comprehensive performance analysis of published SPADs is freely available in http://aqua.epfl.ch/spads.…”

“…An alternative to this approach is the use of a memory of minimum size, 1 bit, or an analog counter. A similar design to Richardson's [30], designed in high-voltage CMOS process by Wu [94], has resulted in a wider PDP profile due to the use of lightly doped high-voltage p-well. Figure 8.10 plots the PDP of various DSM CMOS SPADs in full isolation, as reported in the literature.…”

Dynamic Range Extension of a SPAD Imager Using Non-Uniformity Correction Techniques

“…So far, a few non-uniformity correction techniques for image sensors, mainly charge coupled devices (CCDs) and CMOS-active pixel sensors (CMOS-APS), have already been proposed. Most of these correction techniques are based on simple dark current subtraction to obtain a dark current corrected image frame [10]- [12]. Alternatively, correlated double sampling (CDS) can be performed to acquire at the beginning of each integration time a new and accurate dark reference [13].…”