Two-dimensional simulation of the effects of grain boundaries on theC–Vcharacteristics of P⁺N polysilicon diodes

Abstract

A two-dimensional numerical code is developed to model the effect of grains boundaries (g.b.) on the capacitance–voltage (C–V) characteristics of polysilicon diodes. The test structures are lateral polysilicon P+N diodes where the thickness of the film tf deposited by the low-pressure chemical vapour deposition method is 700 or 450 nm. The P+ and N dopings were performed by ion implantation using, respectively, boron in a dose of 2 × 1015 cm−2 and phosphorus in two doses of 1014 cm−2 for tf = 700 nm and 5 × 1014 cm−2 for tf = 450 nm. Using scanning electron microscopy, the presence of one grain boundary (g.b.) perpendicular to the metallurgic junction and localized at 100 nm of the interface deposition has been observed. In this work, we particularly investigate the effect of this g.b. on the C–V characteristics. The measured C–V characteristics at 100 kHz and 1 MHz show that the frequency effect is more important in the case of the weakly doped film (tf = 700 nm). A determination of the series resistance gives the profile doping concentration: abrupt (ND = 5.5 × 1018 cm−3) for tf = 700 nm and gradual (slope = 5 × 1025 cm−4) for tf = 450 nm.Using the previous experimental parameters in the two-dimensional simulation, we show that the presence of the perpendicular g.b. can reduce by up to 25% the capacitance of the diode and decreases considerably the VRP voltage that corresponds to the realizing–pinning of the electrostatic potential at the first parallel g.b. This effect is more important when the doping is gradual. The fit of the experimental curves gives, in the weak doping case (tf = 700 nm), the position of the first parallel g.b. (LG1 = 37.5 nm) and the density of the inter-granular trap states (NT = 3.2 × 1012 cm−2). On the other hand, when the doping is relatively strong (tf = 450 nm), the fit shows that the C–V characteristic is dominated much more by the doping profile than by the position of the first grain boundary and the density of the inter-granular trap states.

Intrinsic fluctuations induced by a high-κ gate dielectric in sub-100 nm Si MOSFETs

“…The whole study is based on a meticulous calibration against a conventional n-type 67 nm effective gate length Si MOSFET published by IBM [8]. When SiO 2 is replaced with a high-κ dielectric its amorphous structure tends to crystallise during a thermal process used to fabricate the metal gate electrode creating localised regions with a smaller dielectric constant [7]. Intrinsic parameter fluctuations introduced due to discreteness of charge and matter [4] and the interface roughness [5] are creating problems in scaling of conventional MOSFETs with the gate SiO 2 layer to sub-100 nm dimensions.…”