Two-level Pipeline Scheduling of Adiabatic Logic

Varga, L.; Hosszú, Gábor; Kovács, Ferenc

doi:10.1109/isse.2006.365136

Cited by 6 publications

(4 citation statements)

References 6 publications

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“…In addition, the authors also did not model the dual-rail encoding of the input and output signals. After a year, Laszlo Varga et.al, demonstrated a two-level pipelining scheduling of the adiabatic logic design using integer linear programming formulation and a heuristic scheduling [7]. In this work, the authors presented the VHDL description for the functional simulation of the synthesized adiabatic datapath along with the non-adiabatic portion of the digital system.…”

Section: Motivationmentioning

confidence: 99%

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

2019

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The design and functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using function declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioral VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ringcounter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach.

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Section: Motivationmentioning

confidence: 99%

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

2019

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“…A year later, Laszlo Varga et.al. [7] described two-level pipelining and scheduling of adiabatic logic. This approach mainly focussed on producing a pipeline schedule of the power-clock behaviour of the adiabatic logic only for a single-rail scheme.…”

Section: Introductionmentioning

confidence: 99%

A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits

Maheshwari

Bartlett

Kale

2021

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a Hardware Description Language (HDL) based modelling approach for 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit's invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the proposed approach were done on the ISO-14443 standard benchmark circuit, a 16-bit Cyclic Redundancy Check (CRC) circuit. The system modelled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability for the design and verification of large adiabatic systems.

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“…Their work included the description of logic blocks that required 4-phase clocking scheme but did not model the dualrail encoding and use one global clock net instead of 4-phase power-clock for cascade designs. A year later, Laszlo Varga et.al, described two-level pipelining scheduling of adiabatic logic using integer linear programming formulation and a heuristic scheduling [6]. The authors presented the VHDL description for functional simulation of the synthesized adiabatic datapath together with the non-adiabatic part of the digital system.…”

Section: Introductionmentioning

confidence: 99%

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design

Maheshwari

Bartlett

Kale

2018

2018 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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In comparison to conventional CMOS (nonadiabatic logic), the verification of the functionality and the low energy traits of adiabatic logic techniques are generally performed using transient simulations at the transistor level. However, as the size and complexity of the adiabatic system increases, the amount of time required to design and simulate also increases. Moreover, due to the complexity of synchronizing the power-clock phases, debugging of errors becomes difficult too thus, increasing the overall verification time. This paper proposes a VHSIC Hardware Descriptive Language (VHDL) based modelling approach for developing models representing the 4phase adiabatic logic designs. Using the proposed approach, the functional errors can be detected and corrected at an early design stage so that when designing adiabatic circuits at the transistor level, the circuit performs correctly and the time for debugging the errors can substantially be reduced. The function defining the four periods of the trapezoidal AC power-clock is defined in a package which is followed by designing a library containing the behavioral VHDL models of adiabatic logic gates namely; AND/NAND, OR/NOR and XOR/XNOR. Finally, the model library is used to develop and verify the structural VHDL representation of the 4-phase 2-bit ring-counter and 3-bit updown counter, as a design example that demonstrates the practicality of the proposed approach.

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Two-level Pipeline Scheduling of Adiabatic Logic

Cited by 6 publications

References 6 publications

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits

VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design

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