Two modified SVPWM algorithms for common‐mode voltage reduction in eight‐switch three‐phase inverters

Abstract

The relationship between common-mode voltages (CMVs) and switching states in the post-fault reconfigured topology of the threelevel neutral-point-clamped inverter with open-circuit fault in a leg, which is named eight-switch three-phase inverter (ESTPI), is revealed, and based on that, two modified space vector pulse-width modulation (M-SVPWM) algorithms for the CMV reduction in the ESTPI are proposed. The maximum CMV of the ESTPI with two proposed M-SVPWM algorithms is only half of that with two conventional SVPWM algorithms. Experimental results have shown the effectiveness of two proposed M-SVPWM algorithms.

A Fifteen Level Inverter Topology for Grid Connected Applications

“…Multilevel inverter designed [1] with minimization of switching frequency. Space vector modulation technique most effective technique for minimization switching frequency and increasing reliability, efficiency, decreasing complexity.…”

Finite-Set Model Predictive Control for Eight-Switch Three-Phase NPC Converter with DC-Link Voltages Fluctuation Suppression

“…However, the switching devices of three-level NPC are inevitably damaged during the grid fault [7]. In that sense, the power quality will be deteriorated, and the whole system has a destabilizing impact.…”

Improved switching‐table‐based DTC strategy for the post‐fault three‐level NPC inverter‐fed induction motor drives

“…1a [9] is a promising option as the post-fault reconfigured topology of the 3L-NPC inverter under the open-circuit fault occurring in a leg, and it has attracted more and more attention in recent years [9][10][11][12][13][14][15][16][17]. At present, several pulse-width modulation (PWM) methods for the ESTPI have been proposed [9][10][11][12][13][14]. A sinusoidal pulse-width modulation (SPWM) method with two π/3 phase shifted modulating waves for the ESTPI has been proposed in [12].…”

“…Therefore, the topology called eight‐switch three‐phase inverter (ESTPI) presented in Fig. 1 a [9] is a promising option as the post‐fault reconfigured topology of the 3L‐NPC inverter under the open‐circuit fault occurring in a leg, and it has attracted more and more attention in recent years [9–17]. At present, several pulse‐width modulation (PWM) methods for the ESTPI have been proposed [9–14].…”

“…Two different space‐vector pulse‐width modulation (SVPWM) methods based on different basic voltage vectors provided by the ESTPI have been investigated in [10, 11], and the relationship between these two different SVPWM methods has also been revealed in [13]. Moreover, two modified SVPWM algorithms for common‐mode voltage reduction were proposed in [14]. However, the above‐mentioned PWM methods do not take the imbalance of dc‐link capacitor voltages into consideration.…”