Two-phase synchronization with sub-cycle latency

Dobkin, Rostislav; Ginosar, Ran

doi:10.1016/j.vlsi.2008.11.006

Cited by 13 publications

(8 citation statements)

References 31 publications

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“…Verbitsky [6] has described a four‐stage mesochronous synchroniser that provides lower latency and full throughput. Dobkin and Ginosar [7] also proposed two synchronisers that are based on two‐phase protocols. The first one is a low‐latency two‐flip‐flop design and the other one uses a sub‐cycle latency locally delayed latch synchroniser.…”

Section: Literature Reviewmentioning

confidence: 99%

Timing variation aware dynamic digital phase detector for low‐latency clock domain crossing

Khalid

Hasan

Sharif

et al. 2014

IET Circuits, Devices & Systems

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This study presents a digital phase detector-based approach for estimating and synchronising phase variations between clock domains. Instead of waiting for the resolution of metastability (with finite probability of failure), the authors propose a metastability avoidance algorithm, based on a sampling method for asynchronous signals. The results, using 90 nm inovation for high performance microelectronics (IHP) technology, show that the proposed design is about 1.5 times faster and provides a 35% improvement in Energy-Delay Product compared with the state-of-the-art approaches. Moreover, it completely prevents metastability failures.

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Section: Literature Reviewmentioning

confidence: 99%

Timing variation aware dynamic digital phase detector for low‐latency clock domain crossing

Khalid

Hasan

Sharif

et al. 2014

IET Circuits, Devices & Systems

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“…Moreover, the network is more complicated to design. Given that crossing a f domain only adds about 2 ns [12], we choose the simple, single f domain for the network. Hence, when clusters within an ensemble communicate, they cross f domains.…”

Section: Rationale: Simplicity and Effectivenessmentioning

confidence: 99%

EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing

Karpuzcu

Sinkar

Kim

et al. 2013

2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)

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“…Two-phase operation mode can be triggered to work at rising edge and falling edge of the request signal. So its working speed is much higher than that of four-phase operation mode [10] . But two-phase protocol does not fit function module design due to its high complexity; therefore, it is more preferable for communications between asynchronous routers.…”

Section: Introductionmentioning

confidence: 97%

Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips

Guan

Tong

Yang

2010

J. Comput. Sci. Technol.

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For the purpose of solving the shortcomings of low speed and high power consumption of asynchronous wrapper in conventional network on chips, this paper proposes a quasi delay-insensitive high-speed two-phase operation mode asynchronous wrapper. The metastable state in sampling data procedure can be avoided by detecting the write/read signal, which can be used to stop the clock. Empty/full level of the registers can be determined by detecting the pulse signal of the two-phase asynchronous register, and then control the wrapper to sample input/output data. Sender wrapper and receiver wrapper consist of C elements and threshold gates, which ensure the quasi delay-insensitive characteristics and enhance the robustness. Simulations under different technology corners are implemented based on SMIC 0.18 µm standard CMOS. Sender wrapper and receiver wrapper allow synchronous modules to work at the speed of 3.08 GHz and 2.98 GHz respectively with average dynamic power consumption of 1.727 mW and 1.779 mW. Its advantages of high-throughput, low-power, scalability and robustness make it a viable option for high-speed low-power interconnection of network-on-chip.

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Two-phase synchronization with sub-cycle latency

Cited by 13 publications

References 31 publications

Timing variation aware dynamic digital phase detector for low‐latency clock domain crossing

Timing variation aware dynamic digital phase detector for low‐latency clock domain crossing

EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing

Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips

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