Two-Port SRAM Cell with Improved Write Operation

Abstract

It is well known that in Static Random Access Memory (SRAM) cells configured with single-ended bit lines, whenever a write operation is performed, a write failure may occur. In particular, it is relatively difficult to write a logical '1' to a cell if the cell currently stores a logical '0'. It is thus necessary to provide a method of resolving write failures in memory cells. In this paper, a novel seven-transistor (7T) two-port SRAM cell incorporating an assist circuit is proposed. Wherein, the assist circuit is used to deal with the memory cell failures. During a write operation, this circuit is activated to connect a diode-connected transistor to the source of the drive transistor located near to the write bit line. Accordingly, it can provide an efficient solution to the writing '1' issue to improve write operations in this manner. Simulation results for the proposed cell design confirm that there is a conspicuous improvement over the conventional two-port SRAM cells, and fast writing also can be achieved.