Physical delay models entirely based upon device equations for small-geometry CMOS inverters with RC tree interconnection networks are presented. Through extensive comparisons with SPICE simulation results, it is shown that the maximum relative error in delay-time calculations using the developed model is within 15% for 1.5-pm CMOS inverters with RC tree interconnection networks. Moreover, the model has a wide applicable range of circuit and device parameters. Based upon the developed models and the mathematic optimization method, an experimental sizing program is constructed for speed improvement of interconnection lines and trees. In this program, given the size of the input logic gate and its driving interconnection resistances, capacitances, and structures, users can choose one of four speed improvement techniques and determine the suitable sizes and/or number of drivers/ repeaters for a minimum delay. The four speed improvement techniques use minimum-size repeaters, optimal-size repeaters, cascaded input drivers, and optimal-size repeaters with cascaded input drivers to reduce the interconnection delay. It is found from the sizing results of the experimental program that the required tapering factor in cascaded drivers is not e (the base of the natural logarithm) but a value in the range of 4-8. Moreover, adding a small number of drivers/repeaters with large sizes is more efficient in reducing the interconnection delay. It is also shown that the technique of optimal-size repeaters with cascaded input drivers can lead to the lowest delay.

No abstract

No abstract

In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a write operation, by means of sizing the driver transistor close to bitline to resolve the write '1' issue. In addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid unnecessary power consumption. Finally, with the standby start-up circuit design, the cell can switch to the standby mode quickly, thereby reduce leakage current in standby.

delay t i m e [171. Based upon t h e c o n s i d e r a t i o n s of 1) t h e characteristic-waveform e f f e c t ; 2) t h e i n i t i a l -d e l a y e f f e c t ; 3 ) t h e short-channel (1.5pm) logic-gate e f f e c t s ; 4) t h e pole-zero e f f e c t r a t h e r t h a n t h e p o l e e f f e c t only; and 5) t h e combined l a r g e -s i g n a l e q u i v a l e n t c i r c u i t o f g a t e s and i n t e r c o n n e c t i o n l i n e s , a new modeling approach f o r short-channel CMOS l o g i c g a t e s with i n t e r c o n n e c t i o n l i n e s has been developed. Extensive comparisons between model c a lc u l a t i o n s and SPICE simulations have shown t h a t t h e a n a l y t i c model h a s a maximum e r r o r o f 16% on t h e delay t i m e s f o r CMOS i n v e r t e r s with i n t e r c o n n e c t i o n s o f d i f f e r e n t R and C values and s e c t i o n numbers, and w i t h d i f f e r e n t g a t e s i z e s , device parameters, and even i n p u t e x c i t a t i o n waveforms. Reasonable accuracy, wide a p p l i c a b l e range, and high computation e f f i c i e n c y make t h e developed timing models q u i t e a t t r a c t i v e i n MOS V I S I timing v e r i f i c a t i o n and auto-sizing.