Single-Port Five-Transistor SRAM Cell with Reduced Leakage Current in Standby

Abstract

In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a write operation, by means of sizing the driver transistor close to bitline to resolve the write '1' issue. In addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid unnecessary power consumption. Finally, with the standby start-up circuit design, the cell can switch to the standby mode quickly, thereby reduce leakage current in standby.

Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature

“…The architecture of 9T SRAM cell consists of the 6T write cell with 3 additional transistors for the read circuit, as shown in Fig. 3 [13]. Write operation is identical to that of the 6T circuit.…”

“…The storage nodes are accessed using pass-transistors for write, and sometimes read, operations. Existing 6T [11], 8T [12], 9T [13], and 10T [14] SRAM cells require pre-charging of the bit-lines (BL), or read bit-line (RBL) in some cases, during read operation and based on the stored values, one of the bit-lines is discharged. This pre-charging process requires additional circuitry and increases the read delay of the SRAM cell.…”