In this paper, a novel low-power dual edge-triggered (DET) D-type flip-flop is proposed. This design achieves dual edge-triggered with two parallel data paths work in opposite phases of the clock single. Among them, a latch circuit structure employs differential input data signals which deposits very little capacitance on the clock line is accomplished. For fair comparison, four previously reported DET flipflops along with the proposed DETFF (DET flip-flop) are compared in terms of power consumption and power-delay product (PDP), under different data activities and different data rates. Several HSPICE simulation results show that the proposed DETFF is superior in power reduction at different parameters as compared to the existing DETFFs. Hence, the proposed DETFF is well suited for low power applications.

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In this paper, a new single-port five-transistor (5T) Static Random Access Memory (SRAM) cell with integrated read/write assist is proposed. Amongst the assist circuitry, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a write operation, by means of sizing the driver transistor close to bitline to resolve the write '1' issue. In addition, associated with a two-stage reading mechanism to increase the reading speed and to avoid unnecessary power consumption. Finally, with the standby start-up circuit design, the cell can switch to the standby mode quickly, thereby reduce leakage current in standby.

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