The signal delay in interconnection lines considering the effects of small-geometry CMOS inverters

Shiau, Ming-Chuen; Wu, Ching‐Yuan

doi:10.1109/31.52736

Cited by 8 publications

(4 citation statements)

References 17 publications

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“…2. This pi network representation is quite close to the actual case [5] and gives us a very close approximation of signal propagation at node B in fig. 2(a).…”

Section: Figure 1 Block Diagram Of a Memory With A Divided Core And supporting

confidence: 63%

Architecture and design of a high performance SRAM for SOC design

Singh¹,

Azmi²,

Agrawal³

et al.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

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“…2. This pi network representation is quite close to the actual case [5] and gives us a very close approximation of signal propagation at node B in fig. 2(a).…”

Section: Figure 1 Block Diagram Of a Memory With A Divided Core And supporting

confidence: 63%

Architecture and design of a high performance SRAM for SOC design

Singh¹,

Azmi²,

Agrawal³

et al.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

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“…In MOS integrated circuits, a given logic gate may drive several gates, some of them through long wires whose distributed resistance and capacitance may not be negligible. As device dimensions are scaled down, the interconnection delay among logic gates becomes as important as the logic-gate delay in determining the overall speed performance of a VLSI chip [1,2,3]. The delays caused by interconnection wires are then essential in the evaluation of the switching speed of integrated structures and disregarding them would give completely incorrect results.…”

Section: Introductionmentioning

confidence: 99%

A new and accurate interconnection delay time evaluation in a general tree-type network

Deschacht

Dabrin

1995

Proceedings of the 1995 Conference on Asia Pacific Design Automation (CD-ROM) - ASP-DAC '95

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In all recent technologies the delay caused by interconnection wires is essential in the evaluation of the switching speed of integrated structures. Completely wrong results, would result if this were neglected. By considering a distributed RC network to model the interconnection lines, we proposed a new analytical delay time expression for a general tree type network, with full incorporation of technology design parameters. A computationally simple technique is presented and comparisons with HSPICE simulation results show the accuracy of the developed model in timing verification.

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“…As device sizes have been scaled for improved performance and increased density, the interconnect sizing, spacing, and conductor thicknesses have been reduced too [4,31,32]. If all of the dimensions (including conductor thicknesses) in Fig.1 are scaled by S, the capacitance per unit length (cross-section) among the wires remains unchanged.…”

Section: : Interconnect Trendsmentioning

confidence: 99%

Coping with RC(L) interconnect design headaches

Pileggi¹

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

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The signal delay in interconnection lines considering the effects of small-geometry CMOS inverters

Cited by 8 publications

References 17 publications

Architecture and design of a high performance SRAM for SOC design

Architecture and design of a high performance SRAM for SOC design

A new and accurate interconnection delay time evaluation in a general tree-type network

Coping with RC(L) interconnect design headaches

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