Two step evolution strategy for device motif BSIM model parameter extraction

Xiao, Yang; Trefzer, Martin A.; Walker, James Alfred; Bale, Simon J.; Tyrrell, Andy M.

doi:10.1109/cec.2014.6900520

Cited by 3 publications

(4 citation statements)

References 11 publications

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“…Although TCAD simulation avoids effects of factitious factors and improves the accuracy of results, an enormous amount of time is sacrificed for the sake of obtaining accuracy, especially circuit level simulation [5]. To efficiently apply regular device and O shape device layout motif in circuit simulation, SPICE simulation is adopted that also obtain accuracy results and shorter simulating time on circuit level simulation.…”

Section: A Device Layout Motif Physical Simulation and Extractionmentioning

confidence: 99%

“…Beginning with the initial generation in each iteration, an offspring is generated through randomly selecting and modifying the parent gene values [5] [14]. In this experiment, single gene mutation and dynamic gene mutation are separately performed.…”

Section: B Mutationmentioning

confidence: 99%

“…The corresponding device layout motif BSIM models are extracted by a novel two step evolution strategy BSIM model extraction tool [5]. The O shape device layout motif model is extracted from TCAD 50nm technology simulation result and uses specific geometry size (W = 160nm and L = 50nm).…”

Section: A Device Layout Motif Physical Simulation and Extractionmentioning

confidence: 99%

“…In order to achieve [2] this aim, new materials, devices and circuit topologies are suggested to enhance robust product functionality and performance [1]. Alternatively, improving circuit performance through technology optimisation such as layout optimisation has been an interesting avenue of research [2]- [5]. Thus, to investigate the device layout effects on circuit performance, device layout motif using irregular layout is proposed (such as O shape device layout motif that is shown in Fig.…”

Section: Introductionmentioning

confidence: 98%

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Circuit design optimisation using a modified genetic algorithm and device layout motifs

Xiao

Walker

Bale

et al. 2014

2014 IEEE International Conference on Evolvable Systems

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Circuit performance optimisation such as increasing speed and minimizing power consumption is the most important design goal for circuit designers next to correct functionality. This is generally also a very complex problem where, in order to solve it, several factors such as device characteristics, circuit topology, and circuit functionality must be considered. Particularly, as technology has scaled to the atomistic level, the resulting uncertainty factors further affect circuit performance. In this paper, we propose combining a modified genetic algorithm with dynamic gene mutation and device layout motif selection for circuit performance improvement. We explore novel device layout motifs (O shape device) to exploit effects of device layout at the atomistic level in order to improve characteristics of circuits and combine them with a modified GA for automatic circuit optimisation. Additionally, in order to overcome local optima and premature convergence, a dynamic gene mutation rate is performed within the GA. The experimental results show that this methodology can achieve more than 30% delay reduction through mixed combinations of O shape devices and regular devices in a circuit, compared to circuits built of only regular devices. At the same time, the local optima are also reliably avoided due to the dynamic gene mutation.

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Section: A Device Layout Motif Physical Simulation and Extractionmentioning

confidence: 99%

Section: B Mutationmentioning

confidence: 99%

Section: A Device Layout Motif Physical Simulation and Extractionmentioning

confidence: 99%