Two-terminal resistive switches (memristors) for memory and logic applications

Lu, Jiwen; Kim, Ki Wook; Chang,; Gába,

doi:10.1109/aspdac.2011.5722187

Cited by 93 publications

(62 citation statements)

References 35 publications

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“…In the traditional circuit analysis for electronic device, nodal voltage and branch current are employed to describe the device terminal change with time. However, for memory relevant devices such as memristor [13], the nonlinear dynamic with memory effect cannot be explicitly described by these two states and additional internal state variables have to be introduced [12]. These internal state variables can be represented by the external state variables from equivalent circuit point of view [7]- [11] but with increased circuit complexity for simulation.…”

Section: Modified Nodal Analysis Of Nvm Devicesmentioning

confidence: 99%

“…Note that the (11) is a symmetric window function, called Joglekar model [20]; while (12) is an asymmetric window function, called Biolek model [21].…”

Section: Appendix a Dynamic Effect Of Memristormentioning

confidence: 99%

“…In order to consider the new nonvolatile memory devices similarly to how we dealt with CMOS devices by physics based model, one critical perspective is to identify and include the new state variable relevant for the new dynamic behavior of the nonvolatile devices [12]. Note that different from device parameters, a device state variable varies with time under given input signals.…”

Section: Introductionmentioning

confidence: 99%

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Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices

Shang

Wei

2012

IEEE Trans. Circuits Syst. I

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Hybrid integration of CMOS and nonvolatile memory (NVM) devices has become the foundation for emerging nonvolatile memory-based computing. The primary challenge to validate hybrid memory system with both CMOS and NVM devices is to develop a SPICE-like simulator that can simulate the dynamic behavior accurately and efficiently. Since memristor, spin-transfer-toque magnetic-tunneling-junction (STT-MTJ) and phase-change-memory (PCM) devices are the most promising candidates of next generation of NVM devices, it is under great interest in including these new devices in the standard CMOS design flow. The previous approaches either ignore dynamic effect without consideration of internal states for dynamic behavior, or need complex equivalent circuits to represent those devices. This paper proposes a new modified nodal analysis for NVM devices with identified internal state variables for dynamic behavior. As such, compact SPICE-like implementation can be derived for all three new NVM devices in the design of large-scale memory circuits. As demonstrated by a number of examples on hybrid memory circuits with both CMOS and NVM devices, our newly developed SPICE-like simulator can capture dynamic behaviors of memristor, STT-MTJ and PCM devices, and can also reduce CPU runtime by 20-69 times when compared to the previous equivalent circuit based approaches.Index Terms-Internal state variable, memristor, nonvolatile memory (NVM) device, spin-transfer-toque magnetic-tunneling-junction (STT-MTJ), phase-change-memory (PCM), SPICE-like simulation.

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Section: Modified Nodal Analysis Of Nvm Devicesmentioning

confidence: 99%

“…Note that the (11) is a symmetric window function, called Joglekar model [20]; while (12) is an asymmetric window function, called Biolek model [21].…”

Section: Appendix a Dynamic Effect Of Memristormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices

Shang

Wei

2012

IEEE Trans. Circuits Syst. I

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“…In realizing crossbar array for neuromorphic systems, nano-scale two-terminal device such as memristors that can emulate synaptic plasticity with high energy efficiency can be a critical element [12,13]. Memristors mathematically predicted by Leon O. Chua in 1971 as the fourth basic circuit element [14] were experimentally found in 2008 [15].…”

Section: Introductionmentioning

confidence: 95%

New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing

Truong¹,

Min²

2014

JSTS:Journal of Semiconductor Technology and Science

107

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Abstract-In this paper, we propose a new memristorbased crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices. This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively. The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition. For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays. Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture. From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption.

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“…The synapse, which is widely believed the key of neuromorphic networks, can be adjusted as the ionic flow through it. Furthermore, several important synaptic learning behaviors such as STP, LTP and STDP are based on the adaptation of synaptic weight [4][5][6][7][8]. Thus, it is a crying need to find a single structure device that can be used to emulate synaptic learning functions.…”

Section: Introductionmentioning

confidence: 99%

Synaptic learning behaviors achieved by metal ion migration in a Cu/PEDOT:PSS/Ta memristor

Luo

Yuan

et al. 2015

2015 15th Non-Volatile Memory Technology Symposium (NVMTS)

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In this paper, a memristor with structure of Cu/ PEDOT:PSS/ Ta was fabricated at room temperature. The conductance could be modulated incrementally by pulse sequences. The amplitude, width, frequency and quantity of the pulse sequence play important roles in conductance variation, which is similar to the weight of synapses. Several important synaptic learning behaviors such as short-term potentiation (STP), long-term potentiation (LTP) and spike-timing dependent plasticity (STDP) were emulated by this memristor, respectively. It is found that the movement of Cu ions is critical for this device.

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Two-terminal resistive switches (memristors) for memory and logic applications

Cited by 93 publications

References 35 publications

Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices

Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices

New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing

Synaptic learning behaviors achieved by metal ion migration in a Cu/PEDOT:PSS/Ta memristor

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