Type-matching clock tree for zero skew clock gating

Abstract-As the feature size of VLSI circuits scales down and clock rates increases, circuit performance is becoming more sensitive to process variations. This paper proposes an algorithm of symmetrical buffer placement in symmetrical clock trees to achieve zero-skew in theory, as well as robust low skew under process or environment variations. With the completely symmetrical structure, we can eliminate many factors of clock skew such as model inaccuracy, environment temperature and intradie process variations. We devise a new dynamic programming scheme to handle buffer placement and wire sizing under the constraint of symmetry. By classifying the wires by tree levels and defining the level-dependent blockages, the potential candidate points in the gaps of circuit blocks can be fully explored. The algorithm is efficient for minimizing source-sink delay as well as other linear cost functions. Experiments show that our method helps to obtain a balanced design of clock tree with low delay, skew and power.

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“…the wires in a same net always have the same width. To handle these options, we add some modifications on (2).…”

Section: With Buffer and Wire Sizingmentioning

confidence: 99%

“…A typical global clock network structure is a symmetric H-tree with buffers, because symmetrical tree structures are naturally zero-skew. In gated clock trees, a type-matching technique [2] by symmetry is proposed also for the purpose of zero skew.…”

Section: Introductionmentioning

confidence: 99%

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations

Wang

Okamoto

Cheng

2009

2009 IEEE International Conference on Computer Design

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“…As a consequence, the power consumption can be greatly reduced without sacrificing the circuit performance. On the other hand, clock skew minimization [4,5,6] is a critical issue for timing closure. Although the utilization of multiple power modes can greatly reduce the power consumption, the control of clock skew becomes difficult.…”

Section: Introductionmentioning

confidence: 99%

Power-mode-aware buffer synthesis for low-power clock skew minimization

Huang

Cheng

2016

IEICE Electron. Express

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The use of multiple power modes is an effective method for low power. In the clock tree of a multi-power-mode design, power-mode-aware buffers (PMABs) are used for removing the clock skew in different power modes. For each voltage mode of a module, its corresponding delays in the PMABs are designed to align with a global clock latency value. However, the impact of the global clock latency value on the power consumption has not been well studied. In this paper, we demonstrate that different global clock latency values may result in different power consumptions. Based on this observation, we propose a mixed integer linear programming approach to minimize the power consumption by synthesizing the PMABs with the global clock latency value considered. Compared with the previous work, benchmark data show that the proposed approach can reduce 18.31% power consumption of PMABs.

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“…The principal idea is to turn off the idle modules and tree sections in order to cut down the unnecessary switching power. Clock gating can be applied on logic level [11], register-transfer-level level [12] and architecture level [13]. Nevertheless, besides logical information, physical location of the modules should also be taken into account in case wirelength overhead thus power usage waste.…”

Section: Introductionmentioning

confidence: 99%

Clock Network Synthesis with Concurrent Gate Insertion

Chow

Sham

2011

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

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Abstract. In VLSI digital circuits, clock network plays an important role on the total performance of the chip. Clock skew and power dissipation are two major focuses of concerns in the clock network synthesis. During topology generation, the locations of buffer and gate insertion are usually not available. Despite local optimization, the global performance is limited. In this paper, a novel approach of topology generation with concurrent gate insertion is proposed. Meanwhile, a strict clock slew constraint is applied with comprehensive buffer insertion techniques. By clock gating, the switched capacitance of the clock tree is reduced, with acceptable extra cost caused in controller tree. In experimental results it is shown that our approach has good performance on the reduction of both clock skew and power dissipation.

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Type-matching clock tree for zero skew clock gating

Cited by 32 publications

References 12 publications

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations

Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations

Power-mode-aware buffer synthesis for low-power clock skew minimization

Clock Network Synthesis with Concurrent Gate Insertion

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