Ultra High Density IO Fan-Out Design Optimization with Signal Integrity and Power Integrity

Chang, Keng Tuan; Huang, Chun-Yueh; Kuo, Hung-Chun; Jhong, Ming-Fong; Hsieh, Tsun-Lung; Mi-Chun, Hung; Wang, Chen-Chao

doi:10.1109/ectc.2019.00014

Cited by 26 publications

(5 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The accelerating effect of the temperature on EM failure time was more obvious when the current density was 3.5 A/cm 2 , which was 27.51% shorter than 4.5 A/cm 2 at the same temperature difference. In addition, when the current density exceeded 4.5 A/cm 2 , the change in failure time was not obvious, and the maximum critical value of the working current density of micro-bump structures was at 4 A/cm 2 -4.5 A/cm 2 .…”

Section: Discussionmentioning

confidence: 92%

“…By increasing the area of a single package through wafer reconfiguration, the fan-out package breaks the limitation of the number of I/O terminals. Then, the advanced manufacturing process of wafer-level packaging is applied to complete the multilayer rewiring and bump preparation, in addition to cutting and separating, to obtain a package that can interconnect with external electrical properties [ 1 , 2 , 3 ].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study

Tian

Gu²,

et al. 2023

Micromachines

View full text Add to dashboard Cite

To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm2, which was 27.51% shorter than 4.5 A/cm2 at the same temperature difference. When the current density exceeded 4.5 A/cm2, the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm2~4.5 A/cm2.

show abstract

Section: Discussionmentioning

confidence: 92%

Section: Introductionmentioning

confidence: 99%

Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study

Tian

Gu²,

et al. 2023

Micromachines

View full text Add to dashboard Cite

show abstract

“…Fan-out packaging technology utilizes high-density redistributed layers (RDL) for integration between Chiplets, enabling flexible and efficient computing systems. As shown in Figure 10 a, fan-out chip on substrate (FOCoS) technology with ultra-high I/O density is also capable of memory and computation integration [ 53 ]. FOCoS is a fan-out package flip chip mounted on a high-pin-count BGA substrate with a fan-out package RDL.…”

Section: Chiplet-based Processing-in-memory Architecturementioning

confidence: 99%

“… ( a ) FOCoS Technology (reprinted from Ref. [ 53 ], Copyright 2019, with permission from IEEE); ( b ) wafer-level packaging using embedded fine-pitch interconnect chips (reprinted from Ref. [ 54 ], Copyright 2018, with permission from IEEE).…”

Section: Figurementioning

confidence: 99%

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

Tian

Zhao

et al. 2022

Micromachines

View full text Add to dashboard Cite

With the rapid development of 5G, artificial intelligence (AI), and high-performance computing (HPC), there is a huge increase in the data exchanged between the processor and memory. However, the “storage wall” caused by the von Neumann architecture severely limits the computational performance of the system. To efficiently process such large amounts of data and break up the “storage wall”, it is necessary to develop processing-in-memory (PIM) technology. Chiplet combines processor cores and memory chips with advanced packaging technologies, such as 2.5D, 3 dimensions (3D), and fan-out packaging. This improves the quality and bandwidth of signal transmission and alleviates the “storage wall” problem. This paper reviews the Chiplet packaging technology that has achieved the function of PIM in recent years and analyzes some of its application results. First, the research status and development direction of PIM are presented and summarized. Second, the Chiplet packaging technologies that can realize the function of PIM are introduced, which are divided into 2.5D, 3D packaging, and fan-out packaging according to their physical form. Further, the form and characteristics of their implementation of PIM are summarized. Finally, this paper is concluded, and the future development of Chiplet in the field of PIM is discussed.

show abstract

“…Recently, machine learning (ML) techniques have seen considerable success in various engineering fields [13], [14], particularly also in the closely related signal integrity (SI) field [15]- [18]. As a result, researchers have explored the use of ML techniques for the solution of PI and PDN problems [19]- [21]. This includes work utilizing particle swarm optimization, genetic algorithm, and Q-learning to optimize the placement, sizing, and selection of the decoupling capacitors on a PDN [22]- [26].…”

mentioning

confidence: 99%

Machine learning modeling of power delivery networks with varying decoupling capacitors

Liew

Ahmad

Aziz

et al. 2022

IJ-AI

View full text Add to dashboard Cite

<p>This paper presents modeling of power delivery network (PDN) impedance with varying decoupling capacitor placements using machine learning techniques. The use of multilayer perceptron artificial neural networks (ANN) and gaussian process regression (GPR) techniques are explored, and the effects of the hyperparameters such as the number of hidden neurons in the ANN, and the choice of kernel functions in the GPR are investigated. The best performing networks in each case are selected and compared in terms of accuracy using test data consisting of PDN impedance responses that were never encountered during training. Results show that the GPR models were significantly more accurate than the ANN models, with an average mean absolute error of 5.23 mΩ compared to 11.33 mΩ for the ANN.</p>

show abstract

Ultra High Density IO Fan-Out Design Optimization with Signal Integrity and Power Integrity

Cited by 26 publications

References 5 publications

Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study

Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study

Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions

Machine learning modeling of power delivery networks with varying decoupling capacitors

Contact Info

Product

Resources

About