Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs

Kundi, Dur-e-Shahwar; Zhang, Yuqing; Wang, Chenghua; Khalid, Ayesha; O’Neill, Máire; Liu, Weiqiang

doi:10.1109/tetc.2022.3144101

Cited by 36 publications

(23 citation statements)

References 23 publications

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“…In which, #Slice ≈ #LUT 4 for 7 series FPGAs due to 4 LUTs in one Slice [42] and #LUT 8 for UltraScale FPGAs due to 8 LUTs in one Slice [43]. One DSP block can be replaced by 102.4 and 51.2 Slices, and each 36Kb BRAM unit can be substituted by 232.4 and 116.2 Slices for 7 series and UltraScale FPGAs, respectively [26], [44]. The 15th column indicates the data throughput that determines the performance of hardware designs and be measured by the number of bits passing through the NTT module for one second as follows:…”

Section: B Comparison With Related Work and Discussionmentioning

confidence: 99%

“…Prior arts can be classified into two major architectural approaches: (i) in-place NTT architectures that use a single computing module to perform computations iteratively and generate the results after a delay gap [14], [15], [16], [17], [18], [19], [20], [21], [22], [23]; and (ii) fully-pipelined NTT architectures that deploy all stages in series and produce coefficients every clock cycle (CC) [24], [25], [26], [27], [28], [29]. The selection of a design method depends on the parameter setting of the HE schemes, desired throughput rate, and available hardware resources on the target computing platform.…”

Section: A Related Workmentioning

confidence: 99%

“…PipeNTT employed both BRAM and flip-flop as reordering units to rearrange intermediate coefficients. Kundi et al [26] and Zhao et al [27] subsequently proposed high-performance MDC-based NTT accelerators for CRYSTAL-Kyper PQC scheme. The employment of optimized butterfly structure and efficient scheduling result in reducing hardware consumption and improving cryptosystem performance.…”

Section: A Related Workmentioning

confidence: 99%

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Section: B Comparison With Related Work and Discussionmentioning

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Section: A Related Workmentioning

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Section: A Related Workmentioning

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Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption

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“…Utilizing FFT for polynomial multiplication has become prevalent in security applications, including homomorphic encryption [35], [36] and post-quantum cryptography [37], [38]. These works target the multiplication of polynomials over the ring of integers, in which the FFT becomes an NTT.…”

Section: B Fft Acceleratorsmentioning

confidence: 99%

Number Systems for Deep Neural Network Architectures

Alsuhli,

Sakellariou,

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et al. 2024

Synthesis Lectures on Engineering, Science, and Technology

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Quantum computing is an emerging technology on the verge of reshaping industries, while simultaneously challenging existing cryptographic algorithms. FALCON, a recent standard quantum-resistant digital signature, presents a challenging hardware implementation due to its extensive non-integer polynomial operations, necessitating FFT over the ring Q[x]/(x n +1). This paper introduces an ultra-low power and compact processor tailored for FFT/IFFT operations over the ring, specifically optimized for FALCON applications on resource-constrained edge devices. The proposed processor incorporates various optimization techniques, including twiddle factor compression and conflict-free scheduling. In an ASIC implementation using a 22 nm GF process, the proposed processor demonstrates an area occupancy of 0.15 mm 2 and a power consumption of 12.6 mW at an operating frequency of 167 MHz. Since a hardware implementation of FFT/IFFT over the ring is currently non-existent, the execution time achieved by this processor is compared to the software implementation of FFT/IFFT of FALCON on a Raspberry Pi 4 with Cortex-A72, where the proposed processor achieves a speedup of up to 2.3×. Furthermore, in comparison to dedicated state-of-the-art hardware accelerators for classic FFT, this processor occupies 42% less area and consumes 83% less power, on average. This suggests that the proposed hardware design offers a promising solution for implementing FALCON on resource-constrained devices.

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“…Since NTT/INTT calculations are not simultaneously performed, the same architecture is reused to minimize resource consumption. To balance area and speed and match the throughput of data in the subsequent modules, the Radix-2 multipath delay commutator (MDC)based architecture turns out to be the optimal choice [30].…”

Section: Ntt/intt Modulementioning

confidence: 99%

HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining

Khalid

Kundi

et al. 2023

IEEE Trans. Comput.

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CRYSTALS-Kyber (Kyber) was recently chosen as the first quantum resistant Key Encapsulation Mechanism (KEM) scheme for standardisation, after three rounds of the National Institute of Standards and Technology (NIST) initiated PQC competition which begin in 2016 and search of the best quantum resistant KEMs and digital signatures. Kyber is based on the Module-Learning with Errors (M-LWE) class of Lattice-based Cryptography, that is known to manifest efficiently on FPGAs. This work explores several architectural optimizations and proposes a high-performance and area-time (AT) product efficient hardware accelerator for Kyber. The proposed architectural optimizations include inter-module and intra-module pipelining, that are designed and balanced via FIFO based buffering to ensure maximum parallelisation. The implementation results show that compared to state-of-the-art designs, the proposed architecture delivers 25-51% speedups for Kyber's three different security levels on Artix-7 and Zynq UltraScale+ devices, and a 50-75% reduction in DSPs at comparable security level. Consequently, the proposed design achieve higher AT product efficiencies of 19-33%.

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Ultra High-Speed Polynomial Multiplications for Lattice-Based Cryptography on FPGAs

Cited by 36 publications

References 23 publications

Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption

Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption

Number Systems for Deep Neural Network Architectures

HPKA: A High-Performance CRYSTALS-Kyber Accelerator Exploring Efficient Pipelining

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