Ultra-high-throughput Production of III-V/Si Wafer for Electronic and Photonic Applications

Abstract

Si-based integrated circuits have been intensively developed over the past several decades through ultimate device scaling. However, the Si technology has reached the physical limitations of the scaling. These limitations have fuelled the search for alternative active materials (for transistors) and the introduction of optical interconnects (called “Si photonics”). A series of attempts to circumvent the Si technology limits are based on the use of III-V compound semiconductor due to their superior benefits, such as high electron mobility and direct bandgap. To use their physical properties on a Si platform, the formation of high-quality III-V films on the Si (III-V/Si) is the basic technology ; however, implementing this technology using a high-throughput process is not easy. Here, we report new concepts for an ultra-high-throughput heterogeneous integration of high-quality III-V films on the Si using the wafer bonding and epitaxial lift off (ELO) technique. We describe the ultra-fast ELO and also the re-use of the III-V donor wafer after III-V/Si formation. These approaches provide an ultra-high-throughput fabrication of III-V/Si substrates with a high-quality film, which leads to a dramatic cost reduction. As proof-of-concept devices, this paper demonstrates GaAs-based high electron mobility transistors (HEMTs), solar cells, and hetero-junction phototransistors on Si substrates.

Paths to light trapping in thin film GaAs solar cells

“…Many methods have been proposed for improving the cost-effectiveness of GaAs solar cells while maintaining their high conversion efficiency. Amongst the many methods, two are particularly effective and practicable, namely: a) to reuse the GaAs substrate [5][6][7][8], or b) to decrease the thickness of the GaAs active layer [9,10].…”

Stacking defects in GaP nanowires: Electronic structure and optical properties

“…* rubelo@mcmaster.ca 1 arXiv:1810.01194v2 [cond-mat.mtrl-sci] 11 Mar 2019 III-V semiconductor nanowires (NWs) have applications in electronic, optoelectronic, and photonic devices [1]. III-V NWs can be grown epitaxially on Si making integration of III-V optoelectronic devices with Si-based technology possible [2][3][4]. NWs with embedded quantum dots (e.g.GaAs quantum dots in GaP NWs) have shown potential for use in light-emitting diodes (LEDs), lasers and photodetectors [5].Crystal imperfections in 111 oriented III-V NWs is one of the factors that can limit the performance of optoelectronic devices.…”

“…* rubelo@mcmaster.ca 1 arXiv:1810.01194v2 [cond-mat.mtrl-sci] 11 Mar 2019 III-V semiconductor nanowires (NWs) have applications in electronic, optoelectronic, and photonic devices [1]. III-V NWs can be grown epitaxially on Si making integration of III-V optoelectronic devices with Si-based technology possible [2][3][4]. NWs with embedded quantum dots (e.g.…”

Double-gated ultra-thin-body GaAs-on-insulator p-FETs on Si

“…Pre-patterning was carried out in order to achieve a patterned wafer bonding and rapid ELO process. 32 The two separated Y 2 O 3 surfaces were successively exposed to O 2 plasma and immediately bonded to each other via van der Waals force. The two wafers were then pressed together at a pressure of 15 kgf/cm 2 using a wafer bonding machine to enhance the bonding strength.…”

“…30,31 Furthermore, it has strong etching tolerance in HF solutions during the ELO process, facilitating selective etching of AlAs sacrificial layers. 32 The epitaxial structure of the Y 2 O 3 /p-GaAs/Al 0.95 Ga 0.05 As/GaAs substrate was pre-patterned using a 100 × 100 µm 2 photoresist mask and Y 2 O 3 /p-GaAs layers were subsequently etched using HCl and then C 6 H 8 O 7 solutions to expose the Al 0.95 Ga 0.05 As surface. Pre-patterning was carried out in order to achieve a patterned wafer bonding and rapid ELO process.…”