Ultra-low on-resistance high voltage (> 600 V) SOI MOSFET with a reduced cell pitch

Abstract

A low specific on-resistance (RS,on) silicon-on-insulator (SOI) trench MOSFET (metal—oxide—semiconductor—field—effect—transistor) with a reduced cell pitch is proposed. The lateral MOSFET features multiple trenches: two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET). Firstly, the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si; secondly, the oxide trenches cause multiple-directional depletion, which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer. Both of them result in a high breakdown voltage (BV). Thirdly, the oxide trenches cause the drift region to be folded in the vertical direction, leading to a shortened cell pitch and a reduced RS,on. Fourthly, the trench gate extended to the BOX further reduces RS,on, owing to the electron accumulation layer. The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal—oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm, and RS,on decreases from 419 mΩ·cm2 to 36.6 mΩ·cm2. The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

“…Silicon-on-insulator (SOI) is an attractive technology with the merits of reducing leakage current, fast switching, and noise immunity [1][2][3][4][5][6][7] as compared to bulk-Si counterparts. Recently, the buried N-island layer (BNIL) [8] induced charge-accumulated island layer has been reported to insert between the SOI layer and the buried oxide layer (BOX) to enhance the electric field in the BOX.…”

High-voltage SOI lateral MOSFET with a dual vertical field plate

“…[1][2][3][4][5][6] By implanting the oxide trench in the drift region, the power lateral MOSFETs can achieve reduced R on,sp because of the shortened cell pitch. [7][8][9] A two-dimensional analytical model is then developed to explore the physical mechanism of the oxide trench in the silicon-on-insulator (SOI) trench lateral MOSFETs. [10] On the basis of the trench technology, a trench gate is integrated in the oxide trench to obtain a reduced R on,sp .…”

A dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor on a silicon-on-insulator substrate

“…By using a trench filled with oxide in the drift region of the device, the characteristics of the breakdown voltage and the specific on-resistance of reduced surface field (RESURF) laterally diffused metal oxide semiconductors (LDMOS) and LIGBT transistors based on SOI can be improved. [12][13][14][15][16] The aim of this paper is to present a novel dual-gate and dielectric-inserted LTIGBT (DGDI LTIGBT) structure, which combines the merits of the dielectric trench and SOI technologies. Numerical simulations with MEDICI are performed to analyze the proposed DGDI LTIGBT in terms of the onstate characteristics and the temperature performance.…”