Ultra-low power circuit techniques for a new class of sub-mm&lt;sup&gt;3&lt;/sup&gt; sensor nodes

Lee, Yoonmyung; Chen, Gregory; Hanson, Scott; Sylvester, Dennis; Blaauw, David

doi:10.1109/cicc.2010.5617423

Cited by 9 publications

(3 citation statements)

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“…We consider two main application scenarios depending on throughput: a throughput unconstrained application (TUA) and a throughput constrained application (TCA). TUAs are those where data can be sampled, stored and processed [4], whereas TCAs such as real-time DSP applications, require realtime data processing [5].…”

Section: Introductionmentioning

confidence: 99%

System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near- <inline-formula> <tex-math notation="TeX">$V_{t}$</tex-math></inline-formula> Computing

Zhang

Shanbhag²,

Krein³

2014

IEEE Trans. Circuits Syst. II

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This brief proposes to jointly optimize a switched capacitor voltage regulator module (SC-VRM) combined with a compute core to minimize system energy per instruction. Past work seeking to optimize system energy efficiency has focused on separately maximizing SC-VRM efficiency or operating the compute core at its minimum energy operating point (MEOP). We first propose and verify a core-aware SC-VRM energy model, which explicitly accounts for throughput constraints. Second, we perform joint optimization considering throughput unconstrained applications (TUA) and throughput constrained applications (TCAs). We show that, for TUA, the system MEOP (S-MEOP) voltage is different from both the core MEOP (C-MEOP) and VRM maximum efficiency point (V-MEP) voltages, and operating atS-MEOP achieves 12.3% and 21.8% energy savings compared with C-MEOP and V-MEP, respectively. For TCA, S-MEOP is achieved at the same voltage as C-MEOP but different from the voltage for V-MEP, and 38.9% energy savings can be obtained by operating at S-MEOP.Index Terms-DC-DC power converters, design optimization, integrated circuit modeling, switched-mode power supply.

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Section: Introductionmentioning

confidence: 99%

System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near- <inline-formula> <tex-math notation="TeX">$V_{t}$</tex-math></inline-formula> Computing

Zhang

Shanbhag²,

Krein³

2014

IEEE Trans. Circuits Syst. II

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“…Some of them deal with saving energy at MAC (Media Access Control) level [7], [8], [9], others at routing protocols [10], [11], [12], third with dissemination data aggregations or fusion [13], [14], fourth with involving novel architectures that utilize the optimized radio and digital parts [15], [16], [17], fifth employ on-chip power gating in order to reduce the static power loss [18], [19]. To address the problem of power saving within a SN, two promising approaches based on dynamic voltage scaling [20], [21] and power gating [22], [23] are used. The first represents a useful solution for high performance SNs, while the second is effective in SNs operating with low duty-cycle where the SNs alter between off and on states to minimize the energy consumption [22], [16], [17].…”

Section: Introductionmentioning

confidence: 99%

“…In [25] and [26] sensing activities including sensor sensing, sensor logging and actuation are omitted. In [23] a comprehensive energy model for WSN that takes into account all key energy consumption sources within a SN is described. By studying component energy consumption in different SN states the authors in [27] present the energy models of the SN core components.…”

Section: Introductionmentioning

confidence: 99%

Wireless sensor node with low-power sensing

et al. 2014

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Wireless sensor network consists of a large number of simple sensor nodes that collect information from external environment with sensors, then process the information, and communicate with other neighboring nodes in the network. Usually, sensor nodes operate with exhaustible batteries unattended. Since manual replacement or recharging of the batteries is not an easy, desirable or always possible task, the power consumption becomes a very important issue in the development of these networks. The total power consumption of a node is a result of all steps of the operation: sensing, data processing and radio transmission. In most published papers in literature it is assumed that the sensing subsystem consumes significantly less energy than a radio block. However, this assumption does not apply in numerous applications, especially in the case when power consumption of the sensing activity is comparably bigger than that of a radio. In that context, in this work we focus on the impact of the sensing hardware on the total power consumption of a sensor node. Firstly, we describe the structure of the sensor node architecture, identify its key energy consumption sources, and introduce an energy model for the sensing subsystem as a building block of a node. Secondly, with the aim to reduce energy consumption we investigate joint effectiveness of two common power-saving techniques in a specific sensor node: duty-cycling and power-gating. Duty-cycling is effective at the system level. It is used for switching a node between active and sleep mode (with the dutycycle factor of 1%, the reduction of in dynamic energy consumption is achieved). Power-gating is used at the circuit level with the goal to decrease the power loss due to the leakage current (in our design, the reduction of dynamic and static energy consumption of off-chip sensor elements as constituents of sensing hardware within a node of is achieved). Compared to a sensor node architecture in which both energy saving techniques are omitted, the conducted MATLAB simulation results suggest that in total, thanks to involving duty-cycling and power-gating techniques, a three order of magnitude reduction for sensing activities in energy consumption can be achieved.

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Low-Power 60-GHz CMOS Radios for Miniature Wireless Sensor Network Applications

Huang

Wentzloff

2013

Ultra-Wideband and 60 GHz Communications for Biomedical Applications

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Ultra-low power circuit techniques for a new class of sub-mm<sup>3</sup> sensor nodes

Cited by 9 publications

References 45 publications

System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near- <inline-formula> <tex-math notation="TeX">$V_{t}$</tex-math></inline-formula> Computing

System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near- <inline-formula> <tex-math notation="TeX">$V_{t}$</tex-math></inline-formula> Computing

Wireless sensor node with low-power sensing

Low-Power 60-GHz CMOS Radios for Miniature Wireless Sensor Network Applications

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