SummaryColicin B (55 kDa) is a cytotoxic protein that recognizes the outer membrane transporter, FepA, as a receptor and, after gaining access to the cytoplasmic membranes of sensitive Escherichia coli cells, forms a pore that depletes the electrochemical potential of the membrane and ultimately results in cell death. To begin to understand the series of dynamic conformational changes that must occur as colicin B translocates from outer membrane to cytoplasmic membrane, we report here the crystal structure of colicin B at 2.5 Å resolution. The crystal belongs to the space group C2221 with unit cell dimensions a = 132.162 Å, b = 138.167 Å, c = 106.16 Å. The overall structure of colicin B is dumbbell shaped. Unlike colicin Ia, the only other TonB-dependent colicin crystallized to date, colicin B does not have clearly structurally delineated receptor-binding and translocation domains. Instead, the unique N-terminal lobe of the dumbbell contains both domains and consists of a large (290 residues), mostly b b b b -stranded structure with two short a a a a -helices. This is followed by a single long ( ª ª ª ª 74 Å) helix that connects the N-terminal domain to the C-terminal pore-forming domain, which is composed of 10 a a a ahelices arranged in a bundle-type structure, similar to the pore-forming domains of other colicins. The TonB box sequence at the N-terminus folds back to interact with the N-terminal lobe of the dumbbell and leaves the flanking sequences highly disordered. Comparison of sequences among many colicins has allowed the identification of a putative receptorbinding domain.

Sensors with long lifetimes create new applications in medical, infrastructure and environmental monitoring. Due to volume constraints, sensor systems are often capable of storing only small amounts of energy. Several systems have increased lifetime through V DD scaling [1][2] [3]. This necessitates voltage conversion from highervoltage storage elements, such as batteries and fuel cells. Power is reduced by introducing ultra-low-power sleep modes during idle periods. Sensor lifetime can be further extended by harvesting from solar, vibrational and thermal energy. Since the availability of harvested energy is sporadic, it must be detected and stored. Harvesting sources often do not provide suitable voltage levels, so DC-DC up-conversion is required.An 8.75mm3 sensor platform capable of nearly-perpetual operation is proposed. The system includes a 73kHz near-threshold ARM Cortex-M3 core that is powered by two series-connected 1mm 2 solar cells and a Cymbet thin-film solid-state Li battery through an integrated power management unit (PMU) (Fig. 15.8.1). It is suitable for volumeconstrained long-term wireless sensing applications such as intraocular pressure monitoring to detect and track the progression of glaucoma. In the 7.7µW active state, the system collects data from on-chip temperature and capacitance sensors, performs data processing using a 16kb non-retentive SRAM (NR-SRAM) for temporary storage and writes the results to a 24kb retentive SRAM (R-SRAM) (Fig. 15.8.2). Between sensor measurements the system enters a 550pW sleep state by disabling SRAM accesses, power gating the Cortex-M3 and NR-SRAM and switching the PMU to sleep mode. While asleep, the R-SRAM, wakeup controller and sleep timer are powered by a 50Hz switched capacitor network (SCN) that converts energy from the solar cells and battery. If sufficient light is available, solar energy is used to recharge the battery. When the next sensor measurement is scheduled, the wakeup controller switches the PMU to active mode by enabling a 1.2MHz clock for the SCN and a linear regulator (LR). Then power gating is disabled, allowing data collection and processing to begin.The Cortex-M3 achieves 73kHz operation at 400mV and 1MHz at 500mV while running a 64-point DFT program ( Fig. 15.8.3). The energy-optimal point for active mode operation is 2.1µW at 400mV, because further voltage scaling increases total energy consumption due to excessive leakage [4]. During sleep mode, the processor and NR-SRAM are power gated. When the system enters active mode mode, the Cortex-M3 begins program operation with pointers retained through sleep mode that denote the program location and allocated R-SRAM for sensor measurements. The sleep power is 100pW at 400mV and 460pW at 500mV, including R-SRAM, wakeup controller and balloon latch leakage plus sleep timer switching power. The idle processor lifetime is 49 years based on the 12μAh 2.9mm 3 Cymbet battery, which included in the system volume of this work.A custom SRAM was developed to minimize leakage power during sleep mode...

This paper describes an on-die lightweight nanoAES hardware accelerator, fabricated in 22 nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption and decryption on mobile SOCs. Compared to conventional 128 bit AES implementations, this design uses a single 8 bit Sbox circuit along with ShiftRows byte-order data processing to compute all AES rounds in native composite-field. This approach along with a serial-accumulating MixColumns circuit, area-optimized encrypt and decrypt Galois-field polynomials and integrated on-the-fly key generation circuit results in a compact encrypt/decrypt layout occupying 2200/2736 m and lowest-reported gate count of 1947/2090 respectively, while achieving: (i) maximum operating frequency of 1.133 GHz and total power consumption of 13 mW with leakage component of 500 W, measured at 0.9 V, 25 C, (ii) nominal AES-128 encrypt/decrypt throughput of 432/671 Mbps respectively, with peak energy-efficiency of 289 Gbps/W measured at near-threshold operation of 430 mV (11 higher than previously reported implementations), (iii) encrypt/decrypt latencies of 336/216 cycles and total energy consumption of 3.9/2.5 nJ respectively, (iv) wide operating supply voltage range with robust sub-threshold voltage performance of 45 Mbps, 170 W, measured at 340 mV, 25 C and (v) first-reported Galois-field polynomial-based micro-architectural co-optimization, resulting in distinct area-optimized encrypt and decrypt polynomials with up to 9% area reduction at iso-performance.Index Terms-Advanced encryption standard, composite-field polynomial arithmetic, encryption hardware accelerator, lightweight crypto, on-the-fly key-generation, security, ultra-low power AES.

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