Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this work we: (i) review the perspectives of such devices for low-power high-frequency analog IC applications (e.g. GHz operation with sub-0.1 mW power consumption), (ii) discuss and employ a compact TFET device model in the context of the gm/Id integrated analog circuit design methodology, and (iii) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being inter-band tunneling rather than thermionic emission. Starting from TCAD and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs, and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate (DG) TFETs at the 20-nm gatelength node, we conclude that GNR TFETs might promise larger bandwidths at low voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications.Index Terms-Si-FinFETs, Tunnel-FET, ultra low power design, gm/Id method, one-stage common-source amplifier, twostage OTA with Miller effect compensation.