Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014 2014
DOI: 10.7873/date.2014.244
|View full text |Cite
|
Sign up to set email alerts
|

Ultra-low power electronics with Si/Ge tunnel FET

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
9
0

Year Published

2015
2015
2024
2024

Publication Types

Select...
5
2

Relationship

0
7

Authors

Journals

citations
Cited by 20 publications
(9 citation statements)
references
References 0 publications
0
9
0
Order By: Relevance
“…As pointed out in [13][14][15], established design methodologies and tools as well as compact equations representing the device response in all the biasing design space are often required by analog IC designers as a guide for performing optimal circuit design. Here we discuss the gm/Id method and a compact device-model as some of such tools enabling TFET-based analog circuit design.…”
Section: The / Integrated Circuit Design Methods Applied To Tfetsmentioning
confidence: 99%
See 1 more Smart Citation
“…As pointed out in [13][14][15], established design methodologies and tools as well as compact equations representing the device response in all the biasing design space are often required by analog IC designers as a guide for performing optimal circuit design. Here we discuss the gm/Id method and a compact device-model as some of such tools enabling TFET-based analog circuit design.…”
Section: The / Integrated Circuit Design Methods Applied To Tfetsmentioning
confidence: 99%
“…At a given bias current, the DC gain, bandwidth, noise performance and offset improve by increasing the transconductance of the input transistors. Work by Trivedi et al [13] shows that TFETs can reduce the power of analog amplifiers since the same transconductance as in a MOSFET based designs is achieved at lower powers through a higher gm/Id. In the present work a two-stage OTA with Miller effect compensation is designed by using the gm/Id method.…”
Section: Shown Inmentioning
confidence: 95%
“…Energy efficiency represents one of the primary challenges in the development of WBSNs. 30,31 Since communication is the most power-consuming operation for sensor nodes, many current energy-efficient protocols are based on TPC and duty-cycling mechanisms. However, most of these solutions are expensive from both the computational and the memory resources' point of view, and therefore, they result in being hardly implementable on resources constrained devices, such as sensor nodes.…”
Section: Energy Efficiency With Cross-layer Approach In Wbsnsmentioning
confidence: 99%
“…However, most of these solutions are expensive from both the computational and the memory resources' point of view, and therefore, they result in being hardly implementable on resources constrained devices, such as sensor nodes. 31 The PHY layer plays a very important role in WBSN due to the dynamic nature of wireless channel. The power consumption of sensor nodes heavily depends on the PHY layer.…”
Section: Energy Efficiency With Cross-layer Approach In Wbsnsmentioning
confidence: 99%
See 1 more Smart Citation