Ultra-thin Gate Dielectric Plasma Charging Damage in SOI Technology

A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage

“…Plasma-Induced Damage (PID) has been an important concern for equipment vendors and fabs in both traditional SiO2 based and advanced high-k dielectric based processes [1][2][3][4][5][6]. Fig.…”

“…1 illustrates the PID phenomenon that occurs in a gate dielectric during the formation of a metal interconnect. The charge build-up in metal interconnects during the plasma processing steps introduces extra traps in the gate dielectric thereby worsening device reliability mechanisms such as Bias Temperature Instability (BTI) and Time Dependent Dielectric Breakdown (TDDB) [1][2][3]6]. The contiguous metal structure where the charge build up occurs is commonly referred to as an "antenna.…”

“…Circuit designers rely on two methods to prevent the plasma process from imposing noticeable lifetime degradation [6]: (1) ensure that the Antenna Ratio (AR, defined as the area ratio between the antenna and the gate dielectric) does not exceed a given specification or (2) insert antenna diodes to provide other discharge paths. Unfortunately, circuit performance degradation is unavoidable even with the two methods for the following reasons: (1) previous studies have shown a noticeable difference in the PID-induced BTI lifetime for different ARs even within a given specification [3] or (2) inserted antenna diodes increase the capacitance of the metal interconnect, eventually making the circuit slower.…”

“…Existing approaches for characterizing PID effects can be classified into four categories [6]: (1) Measuring the gate-leakage current on fresh devices is a simple and fast method, but suffers from low sensitivity [1][2]. (2) Measuring the TDDB under constant voltage stress is accurate and provides higher sensitivity, but requires a long test time of over 1000 seconds per sample [1][2].…”

“…(2) Measuring the TDDB under constant voltage stress is accurate and provides higher sensitivity, but requires a long test time of over 1000 seconds per sample [1][2]. (3) Rampedvoltage TDDB test was introduced in [1] to reduce the TDDB test time to 2 seconds per sample, but the main drawback is that the results do not match the standard TDDB results very well.…”