Ultrahigh-Q photonic crystal nanocavities fabricated by CMOS process technologies

Abstract

Abstract:We fabricated photonic crystal high-quality factor (Q) nanocavities on a 300-mmwide silicon-on-insulator wafer by using argon fluoride immersion photolithography. The heterostructure nanocavities showed an average experimental Q value of 1.5 million for 12 measured samples. The highest Q value was 2.3 million, which represents a record for a nanocavity fabricated by complementary metal-oxide-semiconductor (CMOS)-compatible machinery. We also demonstrated an eight-channel drop filter with 4 nm spacing consisting of arrayed nanocavities with three missing air holes. The standard deviation in the drop wavelength was less than 1 nm. These results will accelerate ultrahigh-Q nanocavity research in various areas.

Lasing Dynamics of Optically-Pumped Ultralow-Threshold Raman Silicon Nanocavity Lasers

“…Figure 2 shows the optical properties of the two Raman laser samples obtained under cw excitation. The details of the cw measurement technique can be found in our previous publication [33]. Figures 2(a) and 2(b) show the resonant emission spectra from sample A for the pump mode and the Stokes mode, respectively.…”

Ultrahigh‐Q Photonic Nanocavity Devices on a Dual Thickness SOI Substrate Operating at Both 1.31‐ and 1.55‐µm Telecommunication Wavelength Bands

“…These values are smaller than the record of Q exp for the heterostructure nanocavity, 1.11 × 10 7 obtained at the C‐band, because of the smaller Q design and a larger surface absorption losses (the epoxy mask used for fabricating the dual thickness substrate could induce an additional surface absorption loss for the C‐band cavity) . Although there are several reports for C‐band cavities with a Q exp >2.0 × 10 6 , there is only one report for such an O‐band cavity . The smaller a implies an increased refractive index change that is induced by the random variations in the air hole geometry.…”

“…Regarding the PC pattern on the dual thickness substrate, it can be also written using photolithography. Therefore, we consider that the use of a dual thickness substrate will be applicable to mass production using CMOS fabrication machinery with large wafers . This technical approach can realize the integrated Si photonic chip for O/C bands.…”

“…The dimensions of the Si photonic device in the horizontal plane ( x‐ and y‐ directions) can easily be controlled with a nanometer or sub‐nanometer precision using electron‐beam (EB) lithography or photolithography . On the other hand, the thickness ( z ‐direction) of the top Si layer is difficult to control on the nanometer scale even with chemical mechanical polishing which is the most popular method to thin an Si substrate while maintaining crystal quality and surface cleanliness . Control of the thickness on the nanometer scale is also difficult to achieve with plasma etching, where the damage to the top Si layer may be an additional problem.…”

III–V/Silicon Hybrid Non-linear Nanophotonics in the Context of On-Chip Optical Signal Processing and Analog Computing

“…T 0 , namely 3,200, 2,500, and 500. Unlike suspended PhC cavities which can feature very high Qfactors of several millions [15], not suspended membranes show lower Q-factors, up to more than a couple million in silicon [52]. Looking at the same type of cavity as the ones we use, an intrinsic Q-factor of 10 5 was obtained in a not suspended PhC cavity made of InP [51].…”