Ultralow Defect Density at Sub-0.5 nm HfO₂/SiGe Interfaces via Selective Oxygen Scavenging

Abstract

The superior carrier mobility of SiGe alloys make them a highly desirable channel material in complementary metal-oxide-semiconductor (CMOS) transistors. Passivation of the SiGe surface and the associated minimization of interface defects between SiGe channels and high- k dielectrics continues to be a challenge for fabrication of high-performance SiGe CMOS. A primary source of interface defects is interfacial GeO . This interfacial oxide can be decomposed using an oxygen-scavenging reactive gate metal, which nearly eliminates the interfacial oxides, thereby decreasing the amount of GeO at the interface; the remaining ultrathin interlayer is consistent with a SiO -rich interface. Density functional theory simulations demonstrate that a sub-0.5 nm thick SiO-rich surface layer can produce an electrically passivated HfO/SiGe interface. To form this SiO -rich interlayer, metal gate stack designs including Al/HfO/SiGe and Pd/Ti/TiN/nanolaminate (NL)/SiGe (NL: HfO-AlO) were investigated. As compared to the control Ni-gated devices, those with Al/HfO/SiGe gate stacks demonstrated more than an order of magnitude reduction in interface defect density with a sub-0.5 nm SiO -rich interfacial layer. To further increase the oxide capacitance, the devices were fabricated with a Ti oxygen scavenging layer separated from the HfO by a conductive TiN diffusion barrier (remote scavenging). The Pd/Ti/TiN/NL/SiGe structures exhibited significant capacitance enhancement along with a reduction in interface defect density.

Engineering High-k/SiGe Interface with ALD Oxide for Selective GeOx Reduction

“…S6) indicating similar O and Hf peak decay profiles at the SiGe interface unlike with Ni gates which show offsets between O and Hf peak at the interface (Fig. 6a-f) 17 .…”

Understanding the Mechanism of Electronic Defect Suppression Enabled by Nonidealities in Atomic Layer Deposition

“…Elimination of unstable GeO x species may be possible with Si cap layers epitaxially grown on SiGe channels for planar devices; however it may be problematic for gate-all-around devices or FinFETs due to space constraints and the limitation in Si ALDs which may have low mobility due to defects 14 . Previous studies on defect suppression at the gate oxide-SiGe interface have included pre ALD passivation with nitrides [15][16] and sulfur 17 and post ALD selective oxygen scavenging with physical vapor deposited (PVD) gettering metal gates 12,18 . However, the interfaces are still degraded mainly by Ge out-diffusion 13 during ALD at elevated temperatures.…”

“…However, the interfaces are still degraded mainly by Ge out-diffusion 13 during ALD at elevated temperatures. There are also processing challenges, for example the gettering metal inducing a reduction in maximum capacitance by forming thicker gate oxides and PVD being incompatible with nanoscale 3D devices employed 18 . Another approach for defect reduction is selective oxygen scavenging at high temperature (>500C).…”

“…For SiGe substrates, it was shown that post ALD oxidation on low Ge content SiGe (30% to 50%) forms a highly defective SiGeO x interface, and the thickness of the IL decreases for higher Ge composition SiGe (Si 0.69 Ge 0.31 to Si 0.5 Ge 0.95 ) due to suppression of SiO x in the IL 21 . However, DFT and experimental studies shown that formation of an SiO x interface between SiGe and oxide results in an extremely low interfacial defect density on low Ge content SiGe 18 .…”

“…Gate metal and back contacts were formed with Ni thermal evaporation and Al sputtering. Optimized forming gas annealing (5%H 2 /95%N 2 ) was employed in 3 steps 300C-330C-350C for 10 min each, de tails of the very similar MOSCAP fabrication process can be found elsewhere 18 . Electrical characterization of the MOSCAP devices was performed with a Keysight B1500 at 300 K by I-V and multifrequency C-V, G-V measurements from inversion at 2V to accumulation at -2V.…”