Ultralow Specific On-Resistance Superjunction Vertical DMOS With High-$K$  Dielectric Pillar

Luo, Xiaorong; Jiang, Yongheng; Zhou, Kun; Wang, P.; Wang, X. W.; Wang, Q.; Yao, Guo-Liang; Zhang, Bo; Li, Z. J.

doi:10.1109/led.2012.2196969

Cited by 47 publications

(28 citation statements)

References 9 publications

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“…超结结构亦被广泛应用于其他功率器件, 如 IGBT [53] , SBD [54] , 高 K 器件 [55][56][57][58] 等. 早期的纵向超结结构主要通过多次注入和外延之后退火的方式实现, 如英飞凌公司的 CoolMOS 器件 [59] , 意法半导体的 MDmesh 器件 [60] 等.…”

Section: 功率超结器件展望unclassified

Theory and optimization of the power super junction device

Zhang¹,

Zhang²,

Qiao³

et al. 2016

Sci. Sin.-Phys. Mech. Astron.

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Section: 功率超结器件展望unclassified

Theory and optimization of the power super junction device

Zhang¹,

Zhang²,

Qiao³

et al. 2016

Sci. Sin.-Phys. Mech. Astron.

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“…1. The re-drawing of the device in [12] with N-drift region doping of 10 15 cm -3 , N+ sidewall doping of 1×10 18 cm -3 , Pbase doping of 3×10 16 cm -3 , P+, N+ doping of 10 20 cm -3 (a) and its the potential distribution, for the device lengths of 10 μm (b), 20 μm (c), and 30 μm (d), respectively. The drain voltage are 120 V, 240 V, 480 V, and the potential difference between equipotential lines are 5 V, 10 V, 20 V, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…The effect is referred to as HK potential modulation (PM) [9], which has been demonstrated both theoretically [10] and experimentally [11]. Utilizing such effect, a novel device is proposed in [12], which indeed works better than SJ for a lower-BV device. However, as the heavily doped N+ sidewalls are added for smaller R ons , the PM is too weak to deplete the entire drift region fully for the long drift region device with the existence of the N+ sidewalls.…”

Section: Introductionmentioning

confidence: 99%

“…Literatures [9]- [12] took advantages of the PM effect from HK to achieve device performance improvement, however, the potential of the HK is yet to be brought into full play. As HK material exhibits large permittivity, it is capable of activating a strong carrier accumulation effect (CA) in silicon to significantly reduce R ons , which has not been reported according to existing literatures.…”

Section: Introductionmentioning

confidence: 99%

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Investigation of a Novel High-Permittivity Trench MOS Device with Small Figures of Merit

Li¹,

Xiao²

2018

IJCTE

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We propose a vertical high-permittivity trench power metal oxide semiconductor (HKTMOS) device with an alternating N&P drift regions and high-permittivity (HK) trench sandwiched in between. The unique structure guarantees uniform potential distribution for a wide voltage range at the blocking state owing to both the HK potential modulation effect and the superjunction (SJ) charge balance. The specific on-resistance (R ons ) of HKTMOS is orders of magnitude lower than the SJ counterparts in the on-state because of the strong accumulation effect brought by the HK trenches. Although the gate charges also significantly rise because of the accumulation, the figures of merit (FOM) of HKTMOS still decrease considerably compared to the SJ under the same device length condition. An expression for the FOM is derived, demonstrating that the FOM of HKTMOS is proportional to the square of the HK trench depth, which agrees with the simulation results well. The simulation indicates that within the BV range of 500~2000 V, the R ons of HKTMOS is 1~2 orders of magnitude lower than that of SJ, and its FOM is 17.4%~44.1% that of SJ under the same device size condition. Furthermore, HKTMOS also demonstrates better charge imbalance tolerance than SJ.Index Terms-High permittivity, figures of merit, specific on resistance, power MOS.

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“…But, some articles are reported that HK devices suffer from lower switching speed due to higher capacitance effect [7], [8]. The VDMOS reported in [9] with HK pillar describe that device BV increased and alleviates the CI issue. Nevertheless, these improvements are not much satisfying the design requirement of power electronics.…”

Section: Introductionmentioning

confidence: 99%

A Novel Charge-Protection Superjunction-Insulator VDMOS

Naugarhiya¹

2017

IJEEE

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A novel charge-protection Superjunction-Insulator (SJ-I) vertical double diffused MOSFET (SJ-VDMOSs) has been proposed. The proposed analyticalmodel of SJ-I drift layer is verified with the numerical simulation and compared with conventional SJ drift layer model. In the proposed device, we have inserted very thin (100nm) insulator pillar between two consecutive SJ pillars for charge protection and prohibit impurity inter diffusion. This method is optimized Charge Termination (CT) and covers less device area than conventional CT method. In proposed SJ-I devices, the Breakdown Voltage (BV) has been improved by more than 10% with identical area specific ON-resistance (R on A) as compared to conventional SJ devices. Further, we have investigated transfer, output, maximum switching frequency and transient response of SJ-I device.

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Ultralow Specific On-Resistance Superjunction Vertical DMOS With High-$K$ Dielectric Pillar

Cited by 47 publications

References 9 publications

Theory and optimization of the power super junction device

Theory and optimization of the power super junction device

Investigation of a Novel High-Permittivity Trench MOS Device with Small Figures of Merit

A Novel Charge-Protection Superjunction-Insulator VDMOS

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