UltraSPARC-III: a 3rd generation 64 b SPARC microprocessor

Abstract

UltraSPARC-III (US-III) is a 64b 800MHz 4-instruction-issue superscalar microprocessor for high-performance desktop workstation, work group server, and enterprise server platforms. On-chip caches include a 64kB 4-way associative for data (D$), 32kB 4-way associative for instructions (I$), a 2kB 4-way associative data prefetch cache (P$), and a 2kB 4-way associative write (W$). A 90kB on-chip tag array supports the off-chip 8MB unified second-level cache (E$) [1]. The 23M-transistor chip in a 0.15µm, 7-layer metal process consumes 60W from a 1.5V supply [2].The architecture is driven by performance, scalability and compatibility. The design is SPARC V9-compliant, maintaining binary compatibility with all 10,000+ existing SPARC applications [3]. Scalability in two directions is required: 1) taking full entitlement of future process improvements to scale clock rate and 2) off-chip interfaces that enable scaling multi-processor (MP) systems to 1000+ processors. Performance can be achieved in multiple ways. Clock rate is prioritized over IPC improvements, setting a goal of 1.5x the clock rate compared to the previous designs in the same process technology, as well as IPC and compiler improvement goals of 1.15x each, for a doubling of overall performance[4]. This requires different approaches to the micro-architecture, as well as more aggressive circuit and physical design, compared to previous UltraSPARC processors [5,6]. 8 static gates are budgeted for each of the 14 pipeline stages vs. 9 stages and 20 static gates/stage on US-I/II. Timing is more critical in the instruction fetch, integer execution, and floating-point (FP) areas, where dynamic logic is used liberally, than in the memory system.

PDNOC: Partially diagonal network‐on‐chip for high efficiency multicore systems

“…We simulated a multicore processor with 64 (8 × 8) Sun UltraSPARCIII+ cores . Each core is running at 2 GHz, and equipped with private L1 cache (split I + D, 16 KB + 16 KB, 4‐way associative, 64‐byte line, 3‐cycle access delay).…”

A survey of media processing approaches

“…More complex instructions or less frequently used instructions are implemented as sequences of the reduced instruction set. The new generation of processors such as the Sun UltraSPARC (termed as super scalar) [21]- [23] issue up to four instructions simultaneously per cycle. This feature exploits Instruction Level Parallelism.…”

Innovative Verification Techniques Used in the Implementation of a Third-Generation 1.1GHz 64b Microprocessor

“…The chip operates at 1.1GHz to 1.4GHz. The processor core uses a 14-stage pipeline described in [1,2,3] that supports the concurrent launch of up to six instructions which can consist of 2 integer operations, 2 floating point operations, 1 memory operation and 1 control transfer instruction. [5] On-chip, level 1 caches include 64KB 4-way data cache, a 32KB 4-way instruction cache, a 2KB 4-way data prefetch cache, and a 2KB 4-way write cache.…”