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In order to quickly decide which architectural features are to be included infuture processors we have developed a simulation approach that samples benchmark program instruction traces. Rather than simulating an architecture with the entire SPEC92 program suite of more than 100 billion instructions, we simulate using a set of samples of the SPEC92 suite containing less than 1 % of the total instruction trace. Each of our samples contains a short instruction trace that can be simulated quickly. By distributing the simulation of the samples across many workstations we are able to carry out architectural simulations in less than one h a y hour. The sample set is ver@ed to be representative of the complete instruction trace using several metrics. The technique described can be applied to existing architectural models to produce signifcant reductions in simulation time.

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Memory systems for conventional large-scale computers provide only limited bytes/s of data bandwidth when compared to their flop/s of instruction execution rate. The resulting bottleneck limits the bytes/flop that a processor may access from the full memory footprint of a machine and can hinder overall performance. This paper discusses physical and functional views of memory hierarchies and examines existing ratios of bandwidth to execution rate versus memory capacity (or bytes/flop versus capacity ) found in a number of large-scale computers. The paper then explores a set of technologies, Proximity Communication, low-power on-chip networks, dense optical communication, and Sea-of-Anything interconnect, that can flatten this bandwidth hierarchy to relieve the memory bottleneck in a large-scale computer that we call "Hero."

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