A third-generation SPARC V9 64-b microprocessor

Heald, R.; Aingaran, K.; Amir, C.; Ang, M.; Boland, M.; Dixit, P.; Gouldsberry, G.; Greenley, D.; Grinberg, J.; Hart, J.; Horel, T.; Hsu, W.-J.; Kaku, J.; Kim, Chin; Kim, Song; Klass, F.; Kwan, H.; Lauterbach, G.; Lo, R.; McIntyre, H.; Mehta, A.; Murata, D.; Nguyen, Son Truong; Pai, Yet-Ping; Patel, Sanjay J.; Shin, Keun Wook; Tam, Kenway W.; Vishwanthaiah, S.; Wu, Chih-Hang John; Yee, Gin; You, Eileen

doi:10.1109/4.881196

Cited by 59 publications

(23 citation statements)

References 12 publications

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“…We explore wide applicative conditions by considering small, medium and large load and switching activity, i.e. C L = [4,16,64] symmetrical minimum inverters and α sw =[0.10,0.25,0.50] data transition frequency. Clock period duration influencing leakage energy is chosen to be equal to 40FO4 (FO4=18.3ps) and is not varied since we found that FFs rankings do not change significantly even considering a [10-80]FO4 range.…”

Section: Framework For Ffs Analysis and Designmentioning

confidence: 99%

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Physical design aware selection of energy-efficient and low-energy nanometer flip-flops

Alioto

Consoli

Palumbo

2010

2010 International Conference on Microelectronics

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In this paper, a comparison of the most representative flip-flop (FF) topologies in a 65-nm CMOS technology is carried out. For the first time in the literature, local wires capacitances are included in the transistor-level design loop, allowing to reach the actual optimum designs, given the huge impact that local interconnects have on both energy and delay (E-D) of FFs. The investigation permits to identify the most suitable FFs for lowenergy and energy-efficient circuits in nanometer technologies.

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Section: Framework For Ffs Analysis and Designmentioning

confidence: 99%

“…The analyzed IP-EP topologies are the Hybrid Latch FF [14] (HLFF), the Semi-Dynamic FF [15] (SDFF), the UltraSPARC SDFF [16] (USDFF), the Transmission Gate Pulsed Latch [17] (TGPL), the Implicit Push-Pull FF [5] (IPPFF) and the Conditional Precharge FF [18] (CPFF).…”

Section: Analyzed Ffs and Process Normalizationmentioning

confidence: 99%

Physical design aware selection of energy-efficient and low-energy nanometer flip-flops

Alioto

Consoli

Palumbo

2010

2010 International Conference on Microelectronics

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“…Q 0 also uses R 2 , which is ready. The cells (6,2) and (6,4) are set for Q 6 as it uses R 14 and R 12 (produced by Q 2 and Q 4 ) respectively. At time T=2, Q 1 and Q 4 become ready; hence, their columns and scheduler entries are cleared.…”

Section: Matrix-based Schedulersmentioning

confidence: 99%

A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors

Safi

Moshovos

Veneris

2009

2009 International Symposium on Systems, Architectures, Modeling, and Simulation

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This work studies physical-level characteristics of the recently proposed compacted matrix instruction scheduler for dynamically-scheduled, superscalar processors. Previous work focused on the matrix scheduler's architecture and argued in support of its speed and scalability advantages. However, no physical-level implementation or models were reported for it. Using full-custom layouts in a commercial 90 nm fabrication technology, this work investigates the latency and energy variations of the compacted matrix and its accompanying logic as a function of the issue width, the window size, and the number of global recovery checkpoints. This work also proposes an energy optimization that throttles unnecessary pre-charges and evaluations. This optimization reduces energy by 10% and 18% depending on the scheduler size.

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“…Hence, characteristic [1][2][3][4] of Domino circuits have been used in high performance critical circuits like microprocessors [5][6][7]. Dynamic CMOS logic has more advantage in terms of testability.…”

Section: Introductionmentioning

confidence: 99%

TSOP And TSON Testability Analysis And Realizations Of Domino VLSI CMOS Logic

Agrawal¹

2017

IJRASET

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The design for TSOP and TSON fault testability analysis and realizations of Domino VLSI CMOS Logic has been proposed. Domino VLSI CMOS circuits are fast dynamic CMOS circuits and hence suitable for fast and critical circuit applications. The proposed design beat the charge sharing difficulty with enhanced testability using faults TSOP and TSON. Furthermore, increase in number of transistors in the circuits, the proposed scheme shows uninterrupted power decrement in contrast to other schemes.

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A third-generation SPARC V9 64-b microprocessor

Cited by 59 publications

References 12 publications

Physical design aware selection of energy-efficient and low-energy nanometer flip-flops

Physical design aware selection of energy-efficient and low-energy nanometer flip-flops

A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors

TSOP And TSON Testability Analysis And Realizations Of Domino VLSI CMOS Logic

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