Ultrathin Body Germanium-on-Insulator (GeOI) Pseudo-MOSFETs Fabricated by Transfer of Epitaxial Ge Films on III-V Substrates

Yu, Xiao; Zhang, Rui; Kang, Jian; Maeda, Tatsuro; Itatani, Taro; Osada, Takenori; Hata, Masahiko; Takenaka, Mitsuru; Takagi, Shinichi

doi:10.1149/2.0031502ssl

Cited by 7 publications

(5 citation statements)

References 19 publications

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“…So, the perturbation potential is increased as the doping concentration increases, which makes the ionized impurity scattering on carriers enhanced, thus degrading the mobility, as shown in Figure 4. The hole mobility in the high-field regime tends to be consistent because the surface roughness is assumed to be the same, which is similar to that in Reference [29] (for Ge film thickness of 20-60 nm). However, the doping concentration of the channel should not be too low for suppressing the short channel effect OE30 .…”

Section: Simulated Results and Discussionsupporting

confidence: 74%

A physical model of hole mobility for germanium-on-insulator pMOSFETs

Yuan

Liu

et al. 2016

J. Semicond.

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A physical model of hole mobility for germanium-on-insulator pMOSFETs is built by analyzing all kinds of scattering mechanisms, and a good agreement of the simulated results with the experimental data is achieved, confirming the validity of this model. The scattering mechanisms involved in this model include acoustic phonon scattering, ionized impurity scattering, surface roughness scattering, coulomb scattering and the scattering caused by Ge film thickness fluctuation. The simulated results show that the coulomb scattering from the interface charges is responsible for the hole mobility degradation in the low-field regime and the surface roughness scattering limits the hole mobility in the high-field regime. In addition, the effects of some factors, e.g. temperature, doping concentration of the channel and the thickness of Ge film, on degradation of the mobility are also discussed using the model, thus obtaining a reasonable range of the relevant parameters.

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Section: Simulated Results and Discussionsupporting

confidence: 74%

A physical model of hole mobility for germanium-on-insulator pMOSFETs

Yuan

Liu

et al. 2016

J. Semicond.

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“…28) The previous articles about GOI report that the carrier mobility degrades with decreasing GOI thickness in relatively thick (>50 nm) GOI cases. 28,48,49) This study based on GeON, however, indicates a different result. Although we still can not clarify the reason, one possible origin is the starting GeON contains the mobility (and other electrical features) distribution in the depth direction.…”

Section: Layer Transfer and Detachmentmentioning

confidence: 70%

Ge-on-insulator fabrication based on Ge-on-nothing technology

Yamamoto,

Wang,

Loo

et al. 2024

Jpn. J. Appl. Phys.

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Ge-on-Insulator (GOI) is considered a necessary structure for novel Ge-based devices. This paper proposes an alternative approach for fabricating GOI based on the Ge-on-Nothing (GeON) template. In this approach a regular macropore array is formed by lithography and dry etching. These pores close and merge upon annealing, forming a suspended monocrystalline Ge membrane on one buried void. GOI is fabricated by direct bonding of GeON on Si carrier substrates, using an oxide bonding interface, and subsequent detachment. The fabricated GOI shows uniform physical properties as demonstrated using micro-photoluminescence measurements. Its electrical characteristics and cross-sectional structure are superior to those of Smart-CutTM GOI. To demonstrate its application potential, back-gate GOI capacitor and MOSFETs are fabricated. Their characteristics nicely agree with the theoretically calculated one and show typical MOSFET operations, respectively, which indicates promising Ge crystallinity. This method, therefore, shows the potential to provide high-quality GOI for advanced Ge application devices.

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“…Figure 5(b) shows a comparison of I ON /I OFF as a function of SS for the previous studies with UTB JL III-V and Ge p-FETs on Si. [26][27][28]33,34 Although further efforts are required to approach conventional p-FET performance, it is worth emphasizing that the 30 nm-thick JL p-GaAs-OI FET on Si obtained in this study showed the highest I ON /I OFF and potentially the lowest SS value compared to other JL p-FETs.…”

mentioning

confidence: 81%

Double-gated ultra-thin-body GaAs-on-insulator p-FETs on Si

Shim

Kim

et al. 2018

APL Materials

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We demonstrated ultra-thin-body (UTB) junctionless (JL) p-type field-effect transistors (pFETs) on Si using GaAs channels. Wafer bonding and epitaxial lift-off techniques were employed to fabricate the UTB p-GaAs-on-insulator on a Si template. Subsequently, we evaluated the JL FETs having different p-GaAs channel thicknesses considering both maximum depletion width and doping concentration for high performance. Furthermore, by introducing a double-gate operation, we more effectively controlled threshold voltage and attained an even higher ION/IOFF of >106, as well as a low subthreshold swing value of 300 mV/dec.

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Ultrathin Body Germanium-on-Insulator (GeOI) Pseudo-MOSFETs Fabricated by Transfer of Epitaxial Ge Films on III-V Substrates

Cited by 7 publications

References 19 publications

A physical model of hole mobility for germanium-on-insulator pMOSFETs

A physical model of hole mobility for germanium-on-insulator pMOSFETs

Ge-on-insulator fabrication based on Ge-on-nothing technology

Double-gated ultra-thin-body GaAs-on-insulator p-FETs on Si

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