Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates

Ali, Khaled Ben; Neve, Cesar Roda; Gharsallah, Ali; Raskin, Jean‐Pierre

doi:10.1109/ted.2011.2170074

Cited by 38 publications

(11 citation statements)

References 17 publications

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“…On the other hand, the effect of surface charges is negligible with the inclusion of a proper trap-rich layer [7], [8]. We analytically verified that more than 300 nm of a trap-rich layer with an intermediate defect density of can effectively suppress the PSC effect [ Fig.…”

Section: Electromagnetic Simulationmentioning

confidence: 73%

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RF MEMS Passives on High-Resistivity Silicon Substrates

Shim

Raskin

Neve

et al. 2013

IEEE Microw. Wireless Compon. Lett.

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Diverse RF passive devices and microelectro-mechanical systems (MEMS) can be monolithically integrated on a high-resistivity silicon (HR-Si) substrate. However, parasitic surface conduction (PSC) at the interface of HR-Si and a silicon dioxide passivation layer reduces the effective substrate resistivity, which in turn results in deterioration of the device quality factor and non-linearity. Trap-rich HR-Si has been proposed as a low substrate loss alternative, eliminating the problems associated with PSC. However, the full potential of trap-rich HR-Si as a common platform for implementing MEMS passives is not fully explored. In this letter, we evaluate the effectiveness of the trap-rich layer by comparing the frequency response of a number of RF passive devices fabricated on standard and trap-rich HR-Si substrates. In addition, we suggest an electromagnetic (EM) simulation setup that can be used to efficiently and accurately simulate the device performance.

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Section: Electromagnetic Simulationmentioning

confidence: 73%

“…As a result, the and harmonic distortion of RF passives on HR-Si substrate are exacerbated [6]. In order to improve such losses in HR-Si, additional trap-rich layer such as poly-silicon (Psi) or amorphous silicon ( -Si) can be deposited prior to the silicon dioxide deposition step [7], [8].…”

Section: Introductionmentioning

confidence: 99%

RF MEMS Passives on High-Resistivity Silicon Substrates

Shim

Raskin

Neve

et al. 2013

IEEE Microw. Wireless Compon. Lett.

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“…These losses may be traced to the high fixed charges within the oxide layer attracting free carriers near the substrate interface. The trap rich layer was introduced between the interface of the BOX layer and the HR Si substrate to capture the free carriers near the substrate interface, resulting in improved effective resistivity and linearity( (Ali, Neve, Gharsallah, & Raskin, 2011), (Neve & Raskin, 2012) and (Yu et al, 2017)).…”

Section: Benefits Of Globalfoundries 45rfsoi Process For Rf Switchesmentioning

confidence: 99%

Millimeter-wave Antenna Selection Switch using Advanced CMOS Technologies

Tan¹,

Constantin²

2021

2021 International Symposium on Electrical and Electronics Engineering (ISEE)

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I would like to express my sincere thanks to Professor Nicolas Constantin, who gave me the opportunity to study in Canada. Thank you for your dedicated instructions and your enthusiastic support that helped me to have more motivation to complete my thesis.I also want to take this opportunity to thank my labmates at LACIME for all their support and discussions. Especially, I would like to thank Smarjeet for all the good things you taught me from the first day of my study.I would also like to thank Sanjeev for his help during my time at Skyworks Solutions, Inc. Ottawa.Mom, Dad! I am always thankful to you for your unconditional love and support. Finally, I appreciate Skyworks Solutions, Inc. for giving me the opportunity to conduct research and collaborate through the Natural Sciences and Engineering Research Council of Canada (NSERC) Collaborative Research and Development (CRD) Grant. Millimeter-wave antenna selection switch using advanced cmos technologies Hoai Tan PHAM RÉSUMÉ L'objectif principal de ce travail de recherche est de développer un circuit de commutation d'antenne innovant sur circuit intégré (CI) CMOS pour les équipements de communication mobile de cinquième génération (5G).Les objectifs spécifiques sont d'étudier, de concevoir, de simuler, de tester et de valider le fonctionnement du circuit de commutation d'antenne CMOS proposé fonctionnant à 28 GHz. Le circuit de commutation comprend un circuit de commutation SPDT (Single Pole Double Throw) sur une seule puce en technologie CMOS, ainsi que les lignes de transmission nécessaires intégrées dans un stratifié multicouche pour la connexion entre le circuit de commutation sur puce et les deux antennes.La nécessité de la coexistence des technologies RF et ondes millimétriques (par exemple, les émetteurs-récepteurs WLAN dans la bande 5 GHz et les émetteurs-récepteurs de communication machine à machine dans la bande 28 GHz) dans les futurs équipements de communication sans fil impose des défis de conception et d'intégration dans le module Amplificateur de puissance (PA) destiné aux émetteurs frontaux.Un aspect clé est la nécessité d'inclure des fonctions de commutation d'antenne à ondes millimétriques dans le même module PA tout en favorisant la miniaturisation. Cela nécessite une innovation dans la conception et l'intégration de circuits de commutation CMOS à faible perte sur le même CI PA 28 GHz. Cela complique également la conception de la partie frontale de l'émetteur, car elle nécessite des connexions à faible perte à partir du circuit intégré de l'amplificateur de puissance vers différents emplacements d'antenne RF et à ondes millimétriques sur le circuit imprimé (PCB) de l'équipement de communication.Le point de départ est l'étude de la documentation de conception sur une structure de base d'un commutateur d'antenne à ondes millimétriques conçu chez Skyworks Solutions, Inc. Une étude approfondie accompagne cette recherche, à travers des simulations d'architectures et de circuits de commutation de pointe, une revue des techniques proposées dans la l...

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“…The trap-rich literally "freezes" the excess of carriers attracted at the Si surface by the positively charged Si-SiO2 interface (16). The performance of this trap-rich layer has been proven as an effective technique to control transmission line losses with a moderate cost impact while being compatible with industrial SOI wafer fabrication and with the important thermal budget of standard CMOS process (17). To address the different communication standards and functions used in front-end modules, Soitec, the leader in SOI technology, has developed two flavors of RF-SOI products -HR-SOI and Enhanced Signal Integrity TM (eSI) SOI -both of which are compatible with standard CMOS processes.…”

Section: Rfsoi: High Resistivity Substrates Boosting Our Smarphonesmentioning

confidence: 99%

(Plenary) Substrate Innovation for Extending Moore and More than Moore Law

Maleville

2015

ECS Trans.

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Within last 10 years, end markets drastically changed towards mobile connected users. With 8B smartphones to be shipped next 4 years, typical performance/cost KPIs have been evolved towards more demanding PPAC metrics adding power consumption (battery life) and area (from factors) constraints. In this effort to bring more performance, less power or more functionality, innovation or evolution starting from substrates has demonstrated significant successes, such as FDSOI for extension of Moore's law beyond 28nm node. In the field of front end modules (FEM) for smartphones, switch, previously built on AsGa substrates, are now built on RFSOI substrates. Compared to 150mm AsGa wafers, 200mm RFSOI wafers are silicon family wafers and FEM switch are now built in large volume in most foundries, offering very significant die cost advantage. This example can be reproduced for many other application fields or device options where substrate innovation is supporting major improvements. Device scaling: Entering the substrate eraDevice scaling has been since long following so-called Moore's law, doubling transistor density every 2 years, bringing more performance to users with cost improvements. Figure 1 is describing how this was accomplished thru scaling innovation, then material innovation phase. Third phase, labeled as structure innovation in figure 1, is bringing 2 different options: while 1 st option is introducing FinFET, 2nd option relies on FDSOI devices. Figure 1. Technology migration history (1) 10.1149/06605.0013ecst ©The Electrochemical Society ECS Transactions, 66 (5) 13-23 (2015) 13 ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 138.251.14.35 Downloaded on 2015-05-27 to IP

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Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates

Cited by 38 publications

References 17 publications

RF MEMS Passives on High-Resistivity Silicon Substrates

RF MEMS Passives on High-Resistivity Silicon Substrates

Millimeter-wave Antenna Selection Switch using Advanced CMOS Technologies

(Plenary) Substrate Innovation for Extending Moore and More than Moore Law

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