Unbiased roughness measurements: the key to better etch performance

Liang, Andrew; Mack, Chris A.; Sirard, Stephen M.; Liang, C. R.; Liu, Yang; Jiang, Justin; Shamma, Nader; Wise, Rich; Yu, Jengyi; Hymes, Diane

doi:10.1117/12.2297328

Cited by 5 publications

(5 citation statements)

References 1 publication

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“…Furthermore, although roughness could add to measurement noise, instrument noise (not due to roughness) can also be mistaken for feature roughness, requiring unbiased analysis techniques. Recent work aims to identify evaluation methods based on roughness origin and impact 23,24,40 , and instrumentation and procedures 19,24,41 .…”

Section: Metrology Challenges For Complex Ic Device Structuresmentioning

confidence: 99%

Metrology for the next generation of semiconductor devices

Badaroglu²,

et al. 2018

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The semiconductor industry continues to produce ever smaller devices that are ever more complex in shape and contain ever more types of materials. The ultimate sizes and functionality of these new devices will be affected by fundamental and engineering limits such as heat dissipation, carrier mobility and fault tolerance thresholds. At present, it is unclear which are the best measurement methods needed to evaluate the nanometre-scale features of such devices and how the fundamental limits will affect the required metrology. Here, we review state-of-the-art dimensional metrology methods for integrated circuits, considering the advantages, limitations and potential improvements of the various approaches. We describe how integrated circuit device design and industry requirements will affect lithography options and consequently metrology requirements. We also discuss potentially powerful emerging technologies and highlight measurement problems that at present have no obvious solution.

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Section: Metrology Challenges For Complex Ic Device Structuresmentioning

confidence: 99%

Metrology for the next generation of semiconductor devices

Badaroglu²,

et al. 2018

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“…Voltage, current, and frame number were 500 V, 8 pA, and 16 frames, respectively 23 . uLER values were obtained by top-down image collection/analysis with MetroLER software provided by Fractilia 24 , 25 …”

Section: Methodsmentioning

confidence: 99%

“…23 uLER values were obtained by top-down image collection/analysis with MetroLER software provided by Fractilia. 24,25 (a 3 Results and Discussion…”

Section: Unbiassed Ler Measurementmentioning

confidence: 99%

Mask absorber, mask tone, and wafer process impact on resist line-edge-roughness

Ohtomi,

Philipsen,

Welling

et al. 2023

J. Micro/Nanopattern. Mats. Metro.

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.A high-numerical-aperture (NA) extreme ultraviolet lithography (EUVL) system has been highly desired and is now under construction at imec-ASML High NA Laboratory in Veldhoven. However, there are still many challenges to realizing high-volume manufacturing by High NA EUVL. Line edge roughness (LER) mitigation is one of the key elements. In our previous research, we studied how the normalized image log slope (NILS) and resist film thickness affect resist LER by exposure at NA 0.33 on NXE:3400 and S-Litho EUV. However, the mask absorber, mask tone, exposure dose, and postexposure bake (PEB) temperature were not the subject of previous investigations for decreasing LER. They have the potential to mitigate resist roughness such as illumination and resist thickness studied previously. Unbiased LER values of metal oxide resists (MOR) were experimentally measured on a half-pitch (hp) 14 nm line and space under several mask absorber/tonality, dose, and PEB temperature values. Per the mask absorber/tone, the NILS was varied using different illumination shapes. Low-n masks exhibited a higher NILS for the same illumination shape, which resulted in lower resist LER on the wafer. It was also found that the mask tone can contribute to LER mitigation. According to detailed investigations about the mask roughness, mask error enhancement factor, and flare by critical dimension scanning electron microscope (CD-SEM) measurements and S-Litho EUV, the most likely reason for the LER difference is a flare increase given by mask tone changes. From the dose and PEB temperature variation study, dose was apparently more dominant in resisting roughness than PEB temperature.

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“…Voltage, current and frame number are 500 V, 8 pA and 16 frames, respectively [22] . uLER values were obtained by top-down image collection/analysis with MetroLER software provided by Fractilia [23][24] .…”

Section: Unbiassed Ler (Uler) Measurementmentioning

confidence: 99%

Mask absorber/tone and process impact on resist line-edge-roughness

Ohtomi

Philipsen²,

Severi

et al. 2023

Optical and EUV Nanolithography XXXVI

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High numerical-aperture (NA) extreme ultraviolet lithography (EUVL) system has been highly desired [1-3] and is now under construction at imec-ASML high-NA laboratory in Veldhoven. However, there are still many challenges to realize high-volume manufacturing (HVM) by high-NA EUVL; Line edge roughness (LER) mitigation is one of the key elements. In our previous research, we studied how normalized image log slope (NILS) and resist film thickness (FT) affect resist LER by exposure at NA 0.33 on NXE:3400 and S-Litho EUV [4] . However, mask absorber/tone, exposure dose and postexposure bake (PEB) temperature were not focused on for decreasing LER. They have the potential to mitigate resist roughness as illumination and resist thickness also have. Unbiased LER (uLER) values of metal oxide resists (MOR) were experimentally measured on half pitch 14 nm line and space (L/S) under several mask absorber/tonality, dose and PEB temperature. Per mask absorber/tone the NILS was varied by using different illumination shapes. Low-n masks exhibited higher NILS for the same illumination shape, which resulted in lower resist LER on wafer. It was also found that mask tone can contribute to LER mitigation. According to detailed investigations about mask roughness, mask error enhancement factor (MEEF) and flare by CD-SEM measurements and S-Litho EUV, the most likely reason for LER difference is flare increase given by mask tone change. From dose and PEB temperature variation study, dose was apparently more dominant to resist roughness than PEB temperature.

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Unbiased roughness measurements: the key to better etch performance

Cited by 5 publications

References 1 publication

Metrology for the next generation of semiconductor devices

Metrology for the next generation of semiconductor devices

Mask absorber, mask tone, and wafer process impact on resist line-edge-roughness

Mask absorber/tone and process impact on resist line-edge-roughness

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