Under-layer effects for block levels: are they under control?

Shao, Dongbing; Zhang, Bidan; Banerjee, Shayak; Kry, H.; Silva, Anuja De; Kwong, Ranee W.; Chung, Kisup; Lin, Yea-Sen; Leslie, A.

doi:10.1117/12.2029356

Cited by 2 publications

(1 citation statement)

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“…Developerable organic BARC (D-BARC) can be used as an alternative method to reduce the topography effect. Recent D-BARC experimental result show that it can effectivly reduce the wafer topography effect [1]. However according to our experience, D-BARC layer is too sensitive to its thickness, bake temperature and its accordance to photo resist.…”

Section: Introductionmentioning

confidence: 95%

Simple method for decreasing wafer topography effect for implant mask

et al. 2016

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Controlling critical dimension (CD) of implant blocking layers during photolithography has been challenging due to reflection caused by wafer topography. Unexpected reflection which comes from wafer topography makes severe CD variation on mask patterns of implnat layer. Using bottom antireflective coatings(BARCs) can reduce the topography effect, but it could also damage wafer surface during BARCs dry etching. Developable BARCs(D-BARCs) could be alternative solution for wafer topography effect. However there are some issues that should be considered in D-BARCs process such as sensitive temperature control and managing defects. There are also papers introducing model based topography aware OPC as a solution for wafer topography effect implant layer. But building topography aware OPC model is very complex and it takes too much time to build.In this paper, we will introduce experimental results of wafer topography effect using various test patterns and propose a simple method that could effectively reduce wafer topography effect.

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Section: Introductionmentioning

confidence: 95%

Simple method for decreasing wafer topography effect for implant mask

et al. 2016

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Mitigating the influence of wafer topography on the implantation process in optical lithography

et al. 2017

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Residual resist in the gate caused by wafer topography would prevent part of the fins from ion implantation. It is a big concern in semiconductor manufacturing. The optical interference intensity improvement of the region located between two gates induced by substituting the material of the sidewall of the gate with silicon oxide is discussed in this Letter. The relationship between the thickness of silicon oxide and optical intensity at the fin's top is also established from the rigorous coupled wave analysis method. Based on this correlation, the method for mitigating the wafer topography of the implantation process is put forward and evaluated from rigorous numerical simulations. The proposed method requires neither a specific system setup nor an additional etch process, which is a tremendous cost saver in mass production.

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Under-layer effects for block levels: are they under control?

Cited by 2 publications

References 0 publications

Simple method for decreasing wafer topography effect for implant mask

Simple method for decreasing wafer topography effect for implant mask

Mitigating the influence of wafer topography on the implantation process in optical lithography

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