Underfill study for large dice flip chip packages

Lin, A.W.; Cy, Li; Shih, Meng-Kai; Lai, Yi‐Shao; Appelt, Bernd K.; Tseng, Andy

doi:10.1109/icept.2009.5270797

Cited by 4 publications

(1 citation statement)

References 7 publications

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“…The selection of the suitable underfill material is one of the most critical steps in a large die flip-chip packaging assembly. The effects of underfill materials on the reliability of the packages have been investigated [1]. Furthermore, the flow simulations for design and process optimization for underfill were also studied [2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Development of large die assembly process based on simulation and experiments of underfill materials selection

Liu

Chen

et al. 2012

2012 13th International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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Flip-chip ball grid array (FCBGA) packaging was developed to meet the requirements of high I/O density and high electrical performance and the trend of persistent miniaturization of electronic products. Underfill is usually used in flip-chip packaging to fill the gap between the silicon die and the substrate to provide solder bumps protection, compensation of the coefficient of thermal expansion (CTE) mismatch between the silicon die, the solder bumps, and the organic substrate, and prevent fracture failures such as crack of the solder bumps during thermal cycling. The thermalmechanical properties of underfill, such as CTE, Tg (glass transition temperature) and Young's modulus, impact greatly on the reliability of flip-chip packages. This paper presents a study of underfill selection and assembly of large Cu/low-k die (19.2 mm×15.8 mm) with 160 µm bump pitch. Thermal stress simulation was carried out to select suitable underfill material for the Cu/low-k flip chip package. Thermal cycling (TC) test was performed over a range from 125 to -55°C for 1000 cycles to verify the reliability of the package using different underfill materials.

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